Intel BOXDP67BG, Product Manual, Page: 74 / 88

Intel Desktop Board DP67BG Product Guide
74
POST Code Description
PEI Phase Before MRC
11 Set bootmode, GPIO init
12 Early chipset register programming
13 Basic PCH init, discrete device init
14 LAN init
15 Exit early platform init driver
16 SMBUS driver init
17, 18 Entry/Exit to SMBUS execute read/write
19, 1A Entry/Exit to CK505 programming
1B, 1C Entry/Exit to PEI overclock programming
MEC Memory Detection
21 MRC entry point
23 Reading SPD from memory DIMMs
24 Detecting presence of memory DIMMs
27 Configuring memory
28 Testing memory
29 Exit MRC driver
PEI After MRC
2A, 2B Start/finish programming MTRR settings
PEIMs/Recovery
31, 33, 34 Recovery has initiate, load, valid
CPU Initialization (PEI, DXE, SMM)
41-43 Begin to end CPU PEI init
44-46 Begin to end CPU SMM init/relocate bases
47-4C CPU DXE phase begin to end
4D-4F CPU DXE SMM phase begin to end
I/O Buses
50-52 PCI enumeration, allocation, hot plug
58, 59 Resetting USB bus
5A, 5B Resetting SATA bus and all devices
5F Unrecoverable error, start with PIC
Boot Device Selection (BDS)
60-6F BDS driver entry
E4 Entered DXE phase
E7 Waiting for user input
E8 Checking password
E9 Entering BIOS setup
EB Calling legacy option ROMs