Intel BOXDB43LD - B43 Chipset Executive Series, Manual, Page: 49 / 92

Technical Reference
49
Table 16. Chassis Intrusion Header
Pin Signal Name
1 Intruder
2 Ground
Table 17. Front, Rear, and Processor (4-Pin) Fan Header
Pin Signal Name
1 Ground
2 +12 V
3 FAN_TACH
4 FAN_CONTROL
2.2.2.2 Add-in Card Connectors
The board has the following add-in card connectors:
• PCI Express x16:
⎯ Supports PCI Express GEN1 frequency of 1.25 GHz resulting in 2.5 Gb/s each
direction (500 MB/s total). Maximum theoretical bandwidth on interface of
4 GB/s in each direction simultaneously, for an aggregate of 8 GB/s when
operating in x16 mode.
⎯ Supports PCI Express GEN2 frequency of 2.5 GHz resulting in 5.0 Gb/s each
direction (1000 MB/s total). Maximum theoretical bandwidth on interface of
8 GB/s in each direction simultaneously, for an aggregate of 16 GB/s when
operating in x16 mode.
• PCI Express x1: one PCI Express x1 connector. The x1 interface supports
simultaneous transfer speeds up to 250 MB/s of peak bandwidth per direction and
up to 500 MB/s concurrent bandwidth
• PCI Conventional (rev. 2.3 compliant) bus: two PCI Conventional bus add-in card
connectors.
Note the following considerations for the PCI Conventional bus connectors:
• The PCI Conventional bus connectors are bus master capable.
• SMBus signals are routed to the PCI Conventional bus connectors. This enables
PCI Conventional bus add-in boards with SMBus support to access sensor data on
the desktop board. The specific SMBus signals are as follows:
⎯ The SMBus clock line is connected to pin A40.
⎯ The SMBus data line is connected to pin A41.