Intel B5120, Service Manual

Page: 69 / 114

Schematic Diagrams
PARK S3 MAIN GENERIC B - 15
B.Sch
e
m
a
tic D
iag
rams
PARK S3 MAIN GENERIC
G PIO 5
C
7
01
10U
_6.
3V
_0
6
R 691 0_04
1. 8V_REG
DPA
DPB
DVO
I2C
GEN ERAL PURPOS E I/O
DAC1
DAC2
DDC/AUX
THER MAL
PLL/CLOC K
DPC
M 92-S2/M93-S3
M 92- S2/M 93-S3
M 93- S3/M 92-S2
M 93- S3/M 92-S2
M 92- S2/M 93-S3 M 92-S2/M 93- S3
AMD Park XT S3 (A11 )
U 54B
D MIN U S
T2
D PLL_PVD D
AF 14
D PLL_PVSS
AE14
D PLL_VD DC
AD 14
D PLU S
T4
D PC _VSSR #1 / DVPC LK
U 1
D VD AT A_ 7 / D VPCN TL_0
AC 7
D VPC N TL_1 / TX2M_DPC 0N
Y2
D VPC NT L_2/TXC C M_DPC 3N
U5
D PC _VSSR #5/ D VPCN TL_MV0
AA1
D VPC N TL_MV1 / TX1 P_ DPC 1P
Y4
D VD AT A_ 0 / D VPDATA_0
Y 7
D VPD ATA_1 / TX0M_DPC 2N
V2
D PC _VDD 18#1/ D VPD AT10
AC 6
D PC _PVD D / D VPD AT A_ 11
W 6
D VD AT A_ 9 / D VPDATA_12
AD 7
D VPD ATA_13 / TX2 P_ DPC 0P
AA3
D VD AT A_ 8 / D VPDATA_14
AC 8
D PC _VDD 10#1/ D VPD AT15
AA5
D VD AT A_ 12 / D VPDATA_16
AE8
D PC _VDD 10#2/ D VPD AT17
AA6
D VC NTL_ 0/ DVPD ATA_18
AE9
D VD AT A_ 3 / D VPDATA_19
AB4
D VD AT A_ 1 / D VPDATA_2
Y 8
D VD AT A_ 11 / D VPDATA_20
AD 9
D VD AT A_ 2 / D VPDATA_21
AB2
D VD AT A_ 10 / D VPDATA_22
AC 10
D PC _VDD 18#2/ D VPD AT23
AC 5
D VPDATA_3/ TXC C P_ DPC 3P
V4
D VD AT A_ 4 D VPDATA_4
AB7
D PC _VSSR #2 / DVPD AT5
W 1
D VD AT A_ 5 / D VPDATA_6
AB8
DVPD ATA_7 / TX0 P_ DPC 2P
W3
D VD AT A_ 6 / D VPDATA_8
AB9
D VPD ATA_9 / TX1M_DPC 1N
W5
G EN ER I CA
AB13
G EN ER I CB
W 8
G EN ER I CC
W 9
G EN ER I CD
W 7
G EN ER I CE_H PD 4
AD 10
G PIO _0
U 6
G PIO _1
U 10
G PIO _10_R O MSC K
P2
G PIO _11
N 6
G PIO _12
N 5
G PIO _13
N 3
G PIO _14_H PD 2
Y 9
G PIO _15_PW RC N TL_0
N 1
G PIO _16_SSI N
M4
G PIO _17_TH ER MAL _IN T
R 6
G PIO _18_H PD 3
W10
G PIO _19_C TF
M2
G PIO _2
T10
G PIO _20_PW RC N TL_1
P8
G PIO _21_BB_EN
P7
G PIO _22_R O MCSB
N 8
G PIO _23_C LKR EQB
N 7
G PIO _3_SMBD AT A
U 8
G PIO _4_SMBC LK
U 7
G PIO _5_AC _BATT
T9
G PIO _6
T8
G PIO _7_BLO N
T7
G PIO _8_R O MSO
P10
G PIO _9_R O MSI
P4
H 2SYN C
AL13
H PD 1
AC 14
H SYN C
AH2 6
JTAG _TC K
L3
JTAG _TD I
L5
JTAG _TD O
K4
JTAG _TMS
L1
JTAG _TR STB
L6
NC /D D C DATA_AU X3N
AC2 0
N C /D D CC LK_AU X3P
AD2 0
TS_F D O
R 5
TSVD D
AD 17
TSVSS
AC 17
VR EF G
AC 16
VSS1DI
AD2 3
VSS2D I / N C
AC1 9
XTALI N
AM28
XTALO U T
AK28
A2VDD / N C
AE20
A2VD DQ / N C
AE17
A2VSSQ
AE19
AU X1N
AD4
AU X1P
AD2
AU X2N
AD1 1
AU X2P
AD1 3
AVD D
AG2 4
AVSSQ
AE22
B
AH2 4
B2 / N C
AK10
B2B / N C
AL9
BB
AG2 5
C / N C
AH1 2
C OMP / N C
AJ9
D DC 1C LK
AE6
D DC 1D ATA
AE5
D DC 2C LK
AC1 1
D DC 2D ATA
AC1 3
D DC 6C LK
AC1
D DC 6D ATA
AC3
D D C DATA_AU X5N
AD1 6 D D CC LK_AU X5P
AE16
G
AL25
G 2 / N C
AL11
G 2B / N C
AJ11
G B
AJ25
R
AM2 6
R 2 / N C
AM1 2
R 2B / N C
AK12
R 2SET / N C
AG1 3
R B
AK26
R SET
AD2 2
SC L
R 1
SD A
R 3
T X0M_ DPA2N
AG5
TX0P_D PA2P
AG3
T X1M_ DPA1N
AH1 TX1P_D PA1P
AH3
T X2M_ DPA0N
AK1
TX2P_D PA0P
AK3
T X3M_ DPB2N
AM5
TX3P_D PB2P
AK6
T X4M_ DPB1N
AH6
TX4P_D PB1P
AJ7
T X5M_ DPB0N
AL7
TX5P_D PB0P
AK8
TXC AM_ DPA3N
AF 4
TXCAP_D PA3P
AF 2
TXC BM_ DPB3N
AM3 TXCBP_D PB3P
AK5
V2SYN C
AJ13
VD D 1DI
AE23
VD D 2D I / N C
AD1 9
VSYN C
AJ27
Y / N C
AM1 0
N C #1/XO _I N2
AB22
N C #2/XO _I N
AC 22
TESTEN
AF 24
VDD R 4 / D PC D_C ALR
AA12
D VC NTL_ 2 / N C
N 9
D PC _VSSR #3 / GN D
U 3
D PC _PVSS / GN D
V6
D PC _VSSR #4 / GN D
Y 6
D VC NTL_ 1 / N C
L9
MEM_I D
R 693 * 10K_04
SC L 12
LVDS_DDC
H PD _1 47
GENERICA(St ereo displa y sync sig nal)
Unconnected if not use d.
Can also be used as re ference cl ock input
for externa l spread
spectrum fo r TMDS/LVDS .
GPIO20 / GPIO15 FOR
VDDC CORE? ? ? ?
GPIO_21_BB_ EN(Back Bia s (BB) con trol)
When GPIO_2 1_BB_EN = 0 V, then b ack bias is disabled
on the PCB (i.e. BPP = VDDC).
When GPIO_2 1_BB_EN = 3 .3 V, then back bias is enabled
on the PCB (i.e. BPP = VDDC + Of fset).
Can functio n as a GPIO if not re quired for BB control.
D02 add net GPIO21 & R778
for 1.35V power switch.
VBIOS FLASH ROM
A2VD DQ
A2VD D Q
R 778 10 K_ 04
R2SET(DAC2 Reference Resistor)
To set the full scale DAC curren t through a
high preci sion
resistor ( 1%) of 715 O (prelimin ary value)
placed bet ween this
pin and A2 VSSQ.
MUST BE co nnected eve n if not us ed.
DAC2 (TV ) Interface
C 971
0.
1
u_10V
_X
7R
_04
R 779 0_04
I 2C B_SCL 47
I 2C B_SDA 47
.
L94
H CB100 5KF- 121T20
For M93-S3: Use 150 Ohms Pull Down
For M92-S2: Use 0R to VDDR4
.
L91
H C B1005KF -121 T20
Th ese signals must be pu lled
hi gh (to 3.3 V or 5 V) b efore
VD DC is power ed up.
R 692 * 10K_04
R 697 0_04
R 694 * 10K_04
CTF b 20,37
D02
PCI E F U LL TX O U TPUT SW I NG
ENABLE EXTERN AL BI OS R OM
AUD [1 ] AU D [0]
0 0 No audio f unct ion
0 1 Audio f or D isplay Po rt and HD MI if dongle is dete cted
1 0 Audio f or D isplay Po rt only
1 1 Audio f or bo th Display Port and H DMI
SER I AL ROM TYPE OR
PCI E GEN2 EN ABLED
IG N OR E VI P D EVIC E STR APS
VGA ENABLED
PCI E TR AN SMI TTER D E-EMPHASI S EN ABL ED
VG A_ 3.3VS
R 565 10 K_ 04
R 575 * 10K_04
R 571 * 10K_04
R 572 10 K_ 04
R 582 10 K_ 04
R 587 10 K_ 04
T SVSS
R 574 * 10K_04
R 584 * 10K_04
R 567 * 10K_04
R 576 10 K_ 04
R 586 * 10K_04
R 585 * 10K_04
R 566 * 10K_04
R 583 10 K_ 04
R 569 * 10K_04
G PIO 13
G PIO 1
V_H SY
G PIO 5
R O MSI
G PIO 11
G PIO 0
G PIO 12
G PIO 2
H SY NC _D AC 2
VSY N C_D AC 2
R O MCSB
R O MSO
VDD R 4
V_VSY
G EN ERI C C
PIN ST RAPS
GPI O 21 43
1.8V_R EG 15,16, 20
VG A_DD C D ATA 1 2
VG A_DD C C LK 12
If DDC ( I2C master) functional ity is not used
these pi ns
can be a ssociated w ith another DDC interf ace
such as an
LCD or a second (ex ternal) TMD S interface . Can
be used
to suppo rt internal High-bandw idth Digita l
Content
Protecti on (HDCP) f unctionalit y.
G PI O21
The si gnals above can be lef t unconnect ed if not u sed.
For Park-S3: XO_IN and XO_IN2 can be use as
3.3V CLK Input. These poins can be grounded if not
in use.
G PIO 21
XT AL OU T
C 976
0.
1u_10V
_
X
7R
_04
C 975
1U
_6
.3V
_04
C977
10U
_6.
3V
_06
.
L92 H CB1005 KF - 121T20
XTALO U T
R O MSC LK
(1.8V@20mA TSVDD)
(1.8V@45m A VDD1DI)
C
703
0
.1u_10
V
_
X
7
R_04
.
L63
H C B1005KF -121 T20
C
702
1U
_6.
3V
_
04
VG A_R
VG A_G
VD D 1DI
VG A_B
CRT_DDC
G PIO 1
VGA_SMBD AT A
R O MSO
R O MSI
G PIO 0
G PIO 2
VGA_SMBC LK
G PIO 11
G PIO 13
G PIO 12
VDD R 4 1 6
AVSSQ 2
TEST_EN 17
SD A 12
G PIO _23_C LKR EQ B
XTALIN
G ENER IC C
R OMC SB
G PIO 27_TMS
G PIO 26_TC K
G PIO 25_TD I
G PIO 28_TD O
JTAG D EBU G
PO R T
(1.8V @120mA DPLL_PVDD)
HDMI
VGA_R
VGA_B
VGA_G
M92_G PIO 20 45
G PIO 24_TR STB
V_H SY
V_VSY
JTAG_TRSTB( Tap Control ler ASYNC Reset)
TRSTb (Tap Controller ASYNC Rese t)
When TESTEN = 0 V, the n input is a 'don't c are?
JTAG mode: Pulled high (inactive ) to 3.3 V.
R 690 0_04
DD C1 AND AUX1 CAN BE JOI NTED
TO GETHER FOR DUAL DCC/AU X
FU NCTION
RE FER THE DAT ABOOK FOR D ETAIL
SC L
XTALI N
G PIO 7_BLO N
C 974
1U
_6
.3V
_04
1.1V_1 .0V_PWR
(1.1V@300mA DPLL_V DDC)
PLACE VREFG
DIVIDER AND CAP
CLOSE TO ASIC
GPI O7_ BL ON
.
L93
H C B1005KF -121 T20
(1.8V @70mA AVDD)
C
714
1U
_6.
3V
_04
C7 10
18p_50V_N PO _04
R6 11 715_1% _04
S2
S1
2
1
MEMOR Y APER TU RE SIZE SELEC T
35MIL
SD A
35MIL
35MIL
35MIL
35MIL
GPI O _23_C LKREQ B
C
721
1
0U_6
.3V
_06
R604
10K_04
Requires an on boar d TTL buffe r (e.g. LS1 25).
Requires an on boar d TTL buffe r (e.g. LS1 25).
For R /G/B:
One 7 5-O pull-do wn resisto r
close to the con nector bef ore
the f ilter.
Or
Two 1 50-O pull-d own resist ors;
one c lose to the output pi ns on
the G PU and anot her close to the
conne ctor before the filte r.
For R B/GB/BB:
Groun ded right a way. MUST NOT be
conne cted to AVS SQ.
C
723
0.
1u_10V
_X
7R
_04
R590 * 0_04
S5
S1
2 1
. L69 H CB100 5KF- 121T20
R59 3 10K_04
R 610
249_1 %_04
R607 *10K_04
R6 14 4.7K_0 4
R 600
*0 _04
C
705
*
3.
3P
_
50V
_04
. L68 H CB100 5KF- 121T20
C
718
1
0U
_6
.3V
_06
C
700
0.
1
u_10V
_X
7R
_04
R601
150_1%
_04
S3
S1
2 1
C
719
1
U
_6.
3V
_04
PQ 55
MTN 7002Z H S3 G
D
S
.
L67
H C B1005KF -121T 20
C 712
0. 1u_10V_X7 R_04
C
715
0.
1u_
10V
_X
7R
_04
C71 1
18p_50V_N PO _04
G PU_ DMIN U S 20
G PU_ DPLU S 20
X8
H SX840G A_27MHZ
1 2
C70
6
*3.
3
P
_
50V
_04
T herm IN T 20
C
722
1U
_6.
3
V
_04
R 599
10K_04
S6
S1
2 1
S4
S1
2 1
R608 10K_04
.
L62
H C B1005KF -121 T20
C
699
1U
_6
.3
V
_04
R6 13 4.7K_0 4
R609 499_1% _04
R 780 0_04
C
704
*3.
3P
_
50V
_04
C
716
0.
1u_10V
_
X
7R
_04
R
603
15
0
_1%
_0
4
R6 06 1M_04
R 689 * 10K_04
R
602
150_1%
_04
R 598 499_ 1%_04
VGA_3. 3VS 13,20
3.3VS
2 ,10, 11,12, 13, 21,22, 23,2 5,26, 27,28 ,30, 31,32, 33, 34,36, 37, 38,44, 45,4 7
HDMI_DDC
R588 * 150_04
C
720
0
.1u_10V
_X
7R
_04
R59 2 *10K_04
TSVSS
D PLL_PVSS
AVSSQ2
D PLL_PVSS
AVSSQ
D PLL_PVSS
AVSSQ
1. 8V_REG
M92_3. 3VS
VG A_3. 3VS
VG A_ 3.3VS
1. 8V_R EG
1. 8V_R EG
1. 8V_REG
DPLL_ PVD D
1. 1V_1.0 V_ PW R
DPLL_VD D C
VDD 1D I
AVD D
3.3 VS
AVD D
T MD S_D ATA0 47
T MD S_C LO CK# 47
T MD S_D ATA0# 47
G P I O _ 7 _ B L O N ( C o n t r o l s B a c k l i g h t
O n / O f f )
A c t i v e h i g h .
E x t e r n a l 1 0 - k O p u l l - d o w n
r e c o m m e n d e d .
T MD S_D ATA2 47
T MD S_C LO CK 47
T MD S_D ATA1 47
T MD S_D ATA1# 47
T MD S_D ATA2# 47
VG A_G 12
TSVD D
V_VSY 12
V_H SY 12
VG A_B 12
VG A_R 12
GPIO_23_CLKREQB Reserved.
VSY N C _DAC 2
VDD 1D I
R 596 0_04
C
713
1
0U
_6
.3V
_06
1.1V_1. 0V_PW R 13, 15,16, 20
R 826 33_04
U 60
*EN 25P05- 50G CP
CE#
1
SO
2
W P#
3
VSS
4
SI
5
SCK
6
H O LD #
7
VD D
8
D02
R692,R689,R693,R694
chaange to NC for
SAMSUNG VRAM
MEM ID set=0.
C 1031 .1U _16 V_ 04
R 825 33_04
R 827 33_04
R 824 33_04
PAR K_H OLD #
512Kbit
PAR K_VD D_1
R O MSC LK
PAR K_F LASH R O MC SB
R O MSI
R O MSO
N C4
*SH OR T
R 823 4.7 K_ 04
R 822 1K_04
3 .3VS
0.1"~0.5"
C 979
0.
1u_10V
_
X
7R
_04
C 978
1U
_6.
3
V
_04
C 972
10U
_6
.3V
_06
M92_G PIO 15 45
M9 2_3.3VS 13, 16
RSET (DAC 1 Reference Resistor)
To set th e full scal e DAC curre nt
through a high preci sion
resistor (1%) of 499 O placed b etween
this pin and AVSSQ.
M92_3. 3VS
Unconnecte d if DAC2 i s not used;
1.8 V_ REG
C973
10U
_6
.3V
_06
HSY N C_ DAC 2
R 695 0_04
For Park-S3: DNI (NC)
VDD 3 2 1,30, 34,37 ,38, 39,46
C
698
10U
_6
.3V
_06
R 696 0_04
Sheet 14 of 56
PARK S3 MAIN
GENERIC