Errata
22
Specification Update
BH20
IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
Problem:
The IO_SMI bit in SMRAM’s location 7FA4H is set to "1" by the CPU to indicate a
System Management Interrupt (SMI) occurred as the result of executing an instruction
that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly
set by:
•
A SMI that is pending while a lower priority event is executing
•
A REP I/O read
•
A I/O read that redirects to MWAIT
Implication:
SMM handlers may get false IO_SMI indication.
Workaround:
The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH21
Writes to IA32_DEBUGCTL MSR May Fail when
FREEZE_LBRS_ON_PMI is Set
Problem:
When the FREEZE_LBRS_ON_PMI, IA32_DEBUGCTL MSR (1D9H) bit [11], is set,
future writes to IA32_DEBUGCTL MSR may not occur in certain rare corner cases.
Writes to this register by software or during certain processor operations are affected.
Implication:
Under certain circumstances, the IA32_DEBUGCTL MSR value may not be updated
properly and will retain the old value. Intel has not observed this erratum with any
commercially available software.
Workaround:
Do not set the FREEZE_LBRS_ON_PMI bit of IA32_DEBUGCTL MSR.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH22
Address Reported by Machine-Check Architecture (MCA) on L2 Cache
Errors May be Incorrect
Problem:
When an L2 Cache error occurs (Error code 0x010A or 0x110A reported in
IA32_MCi_STATUS MSR bits [15:0]), the address is logged in the MCA address
register (IA32_MCi_ADDR MSR). Under some scenarios, the address reported may be
incorrect.
Implication:
Software should not rely on the value reported in IA32_MCi_ADDR MSR for L2 Cache
errors.
Workaround:
None.
Status:
For the steppings affected, see the Summary Tables of Changes.
