3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
The JTAG configuration scheme overrides all other configuration schemes. The SDM is always ready to accept configuration
over JTAG unless a security feature disables the JTAG interface. JTAG is particularly useful in recovering a device that may be
in an unrecoverable state reached when trying to configure using a corrupted image.
An
nCONFIG
falling edge terminates any JTAG access and the device reverts to the
MSEL
-specified boot source.
nCONFIG
must be stable during JTAG configuration.
nSTATUS
follows
nCONFIG
during JTAG configuration. Consequently,
nSTATUS
also
must be stable.
Unlike other configuration schemes,
nSTATUS
does not assert if an error occurs during JTAG configuration. You must monitor
the error messages that the Intel Quartus Prime Pro Edition Programmer generates for error reporting.
Note:
For Intel Agilex SX devices when you choose to configure the FPGA fabric first, the JTAG chain has no mechanism to redeliver
the HPS boot information following a cold reset. Consequently, you must reconfig the device with the
.sof
file or avoid cold
resets to continue operation.
Debugging Suggestions
Here are some debugging tips for JTAG:
•
Verify that the JTAG pin connections are correct.
•
If JTAG configuration is failing, check that the FPGA has successfully powered up and exited POR. One strategy is to check
the hand shaking behavior between
nCONFIG
and
nSTATUS
by driving
nCONFIG
low and ensuring that
nSTATUS
also
goes low.
•
Verify that the
nCONFIG
pin does not change state during JTAG configuration.
•
Another way to determine whether the device has exited the POR state is to use the Intel Quartus Prime Programmer to
detect the device. If the programmer can detect the Intel Agilex device, it has exited the POR state.
•
If you are using an Intel FPGA Download Cable II, reduce the cable clock speed to 6 MHz.
•
If you have multiple devices in the JTAG chain, try to disconnect other devices from the JTAG chain to isolate the Intel
Agilex device.
•
If you specify the
OSC_CLK_1
as the clock source for configuration, ensure that
OSC_CLK_1
is running at the frequency
you specify in the Intel Quartus Prime software.
•
For designs including the High Bandwidth Memory (HBM2) IP or any IP using transceivers, you must provide a free
running and stable reference clock to the device before device configuration begins. All transceiver power supplies must
be at the required voltage before configuration begins.
3. Intel Agilex Configuration Schemes
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®
Agilex
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Configuration User Guide
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