Intel 8XC251SA, User Manual

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5-11
PROGRAMMING
5.4 BIT INSTRUCTIONS
A bit instruction addresses a specific bit in a memory location or SFR. There are four categories
of bit instructions:
•
SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear
or complement any addressable bit.
•
ANL (And Logical), ANL/ (And Logical Complement), ORL (OR Logical), ORL/ (Or
Logical Complement). These instructions allow ANDing and ORing of any addressable bit
or its complement with the CY flag.
•
MOV (Move) instructions transfer any addressable bit to the carry (CY) bit or vice versa.
•
Bit-conditional jump instructions execute a jump if the bit has a specified state. The bit-
conditional jump instructions are classified with the control instructions and are described
in section 5.5.2, “Conditional Jumps.”
5.4.1 Bit Addressing
The bits that can be individually addressed are in the on-chip RAM and the SFRs (Table 5-5). The
bit instructions that are unique to the MCS 251 architecture can address a wider range of bits than
the instructions from the MCS 51 architecture.
There are some differences in the way the instructions from the two architectures address bits. In
the MCS 51 architecture, a bit (denoted by bit51) can be specified in terms of its location within
a certain register, or it can be specified by a bit address in the range 00H–7FH. The MCS 251
architecture does not have bit addresses as such. A bit can be addressed by name or by its location
within a certain register, but not by a bit address.
Table 5-6 illustrates bit addressing in the two architectures by using two sample bits:
•
RAMBIT is bit 5 in RAMREG, which is location 23H. “RAMBIT” and “RAMREG” are
assumed to be defined in user code.
•
IT1 is bit 2 in TCON, which is an SFR at location 88H.
Table 5-5. Bit-addressable Locations
Architecture
Bit-addressable Locations
On-chip RAM SFRs
MCS
®
251 Architecture 20H–7FH All defined SFRs
MCS 51 Architecture 20H–2FH
SFRs with addresses ending in 0H or 8H:
80H, 88H, 90H, 98H, ..., F8H