Intel 82543GC Specification Update Download Page 23

82543GC Gigabit Ethernet Controller Specification Update 

 

 

 

 

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5.  Register Summary Uses Improper Page Reference Format 

 

Problem

:  

The 82543GC Register Summary  refers to page numbers in the format (11-182, 11-186, 11-188, …) and (10-
162, 10-166, 10-166, …).  

 

The pagination will change to the format (182, 186, 188, …) and (162, 166, 186, …). The actual page numbers 
are correct. 

Affected Docs:  

OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual Rev. 2.01.

 

6.  Change O_EN_CDET Output to NO_CONNECT 

 

Problem

:  

The output labeled O_EN_CDET should be relabeled to NO_CONNECT. The Enable Comma Detect function is 
not present on the 825543GC Gigabit Ethernet Controller. This change affects the Pin Description Tables and 
Signal Name to Electrical Connection Lists.  

 

Comma detection triggers a SERDES device (present in 1000BASE-SX designs) to re-acquire byte 
synchronization, and is used primarily during Auto-negotiation. Comma detection can be asserted on the 
SERDES by permanently connecting the SERDES input to Vcc through an approximately 1K pullup resistor. 
The SERDES will perform the realignment every time it detects a comma character. 

Affected Docs:  

OR-2711 82543GC Gigabit Ethernet Controller Advance Information Datasheet  Rev. 2.01. 

 7.  Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T 

 

Problem

:  

The IEEE standard minimum transmit inter-packet gap is 96 bit times. To achieve that gap requires a 
programmed setting to the IPGT Field in the Transmit Inter packet Gap (TIPG) Register. The actual inter-packet 
gap in MAC data clocks) is the sum of the programmed value and a variable logic synchronization time within 
the device. Use a recommended programming value of 10 for TBI applications and 10 for 10/100/1000BASE-T 
applications to assure that the minimum IPG gap will be met under all synchronization conditions.  

 

The Developer’s Manual currently indicates a programming value of 6 for both fiber and copper 
implementations. This value will change to 10.  In addition to the register listing, section 12.5 Transmit 
Initialization text should change.   

Affected Docs:  

OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual Rev. 2.01.

 

 

8.  Remove Transmit Report Status Sent Function  

Problem

:  

The Transmit Report Status Sent function is not implemented to write back descriptor status when packet data 
goes out on the wire. The Report Packet Sent (RPS) Bit in the transmit descriptor (Bit 4 in TDESC.CMD) is 
Reserved and should be programmed to 0. The related Report Status function (Bit 3 in TDESC.CMD) may be 
used to force transmit descriptor status bytes to be written back to memory as the packet data reaches the 
transmit queue. 

 

Affected text includes 4.3.2 Transmit Descriptor Writeback and references in numerous other sections, including 
the interrupt description text.   

Affected Docs:  

OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual Rev. 2.01. 

9.  Remove Transmit DMA Pre-fetching and Preemption Functions  

 

Problem

:  

The controller does not implement the ability to start transmit descriptor data fetches before finishing the 
previous descriptor. In addition, it does not have the ability to disable DMA preemptions during TCP 

Summary of Contents for 82543GC

Page 1: ...June 18 2004 Revision 2 1 The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current chara...

Page 2: ...t descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definit...

Page 3: ...and 100Mb Operation 13 9 CRS Detection Takes Too Long in MII Half Duplex Mode 13 10 DMA Early Receive Function Does Not Work 13 11 ILOS Bit Copied Incorrectly from EEPROM to Speed Bits 13 12 Gigabit...

Page 4: ...gister RDTR Causes Occasional Lockups 20 38 Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000 20 SPECIFICATION CLARIFICATIONS 21 1 0 70C Ambient Temperature Range 21 2 Receiver Enabli...

Page 5: ...GC Gigabit Ethernet Controller Specification Update 5 REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Date of Revision Revision Description June 18 2004 2 1 Initial Public Re...

Page 6: ...82543GC Gigabit Ethernet Controller Specification Update 6 Note This page is intentionally left blank...

Page 7: ...es will be incorporated in the next release of the specifications Errata are design defects or errors Errata may cause 82543GC device behavior to deviate from published specifications Hardware and sof...

Page 8: ...ed with either QDF number or S spec number A2 Q417 N A FW82543GC or TL82543GC Engineering Samples May be marked two ways with the QDF number and a top mark FW82543GC or without any QDF or S spec numbe...

Page 9: ...Maximum Size Limitation 9 3 X Fixed Late Collision Statistics May Be Incorrect 9 4 X Fixed Some Registers Cannot be Accessed During Reset 10 5 X X X NoFix DAC Accesses May Not Be Interpreted Correctly...

Page 10: ...Page Affected Document 1 X X X Doc Change 0 70C Ambient Temperature Range 19 Datasheet 2 X X X Doc Change Receiver Enabling and Disabling 19 Developer s Manual No A0 A1 A2 Plans DOCUMENTATION CHANGES...

Page 11: ...out data transfer In response the 82543GC controller may attempt another read or write cycle to a different address instead of retrying the same memory location In a PC environment it is possible that...

Page 12: ...karound Bit 0x0D in the EEPROM space at byte 0x0A denotes 64 bit address mapping if cleared to 0 This is the default configuration Program the bit to logic 1 to denote 32 bit address space As an added...

Page 13: ...ated in operating networks however Workaround None Status Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller 10 DMA Early Receive Function Does Not Work Problem...

Page 14: ...tion Do not use the TCP segmentation feature Workaround None Status Some of the errata were corrected in the A1 stepping At least one severe transmit problem was not corrected Intel does not plan to r...

Page 15: ...er 19 Transmit Packet Corruption of Small Packets Problem When the 82543GC Ethernet Controller is transmitting and receiving simultaneously it is possible that short packets will be corrupted before t...

Page 16: ...e problem may not be seen with some link partners particular those that are not in strict IEEE compliance with respect to collisions Implication The 82543GC Gigabit Ethernet Controller cannot be used...

Page 17: ...efault speed setting CTRL SPEED will depend on whether a valid EEPROM is present as determined by the signature bits If a legitimate EEPROM is determined not to be present the controller will use 10b...

Page 18: ...tects any other value it Is supposed to abort processing initialization data and use its defaults instead With this erratum the controller continues processing the EEPROM initialization values even if...

Page 19: ...he following precautions Configure the receive interrupt to occur immediately on end of packet by programming RDTR 0 Configure the descriptor writeback threshold WTHRESH to a value that will not resul...

Page 20: ...ter RDTR is used to delay interrupt notification until a number of microseconds elapse past the last receive packet in a sequence of packets Under high traffic conditions this function can occasionall...

Page 21: ...eiver by programming the Enable EN Bit in the Receive Control Register RCTL The reason is that the disabling enabling operation does not re initialize packet filter logic that demarcates packet start...

Page 22: ...et developer s manual documents indicated in the preface of this spec update 3 Values Programmed to Some Registers While in Reset Do Not Persist Problem This behavior is related to erratum 4 Some Regi...

Page 23: ...Register The actual inter packet gap in MAC data clocks is the sum of the programmed value and a variable logic synchronization time within the device Use a recommended programming value of 10 for TB...

Page 24: ...Transmit Burst Timer Register TBT will be removed from the developer s manual Note Erratum 12 prohibits Gigabit half duplex mode operation Affected Docs OR 2710 82543GC Gigabit Ethernet Controller De...

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