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Intel 82491 CACHE SRAM, User Manual

The Intel 82491 CACHE SRAM is a high-performance memory module designed to enhance system performance. To learn how to maximize its capabilities, download the User Manual for free from manualshive.com. This comprehensive manual provides step-by-step instructions on installation and configuration, ensuring optimal use of this powerful product.

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Summary of Contents for 82491 CACHE SRAM

Page 1: ......

Page 2: ...er and business computing products Over the last two and a half decades Intel s business has evolved and today the company s focus is on delivering an extensive line of component module and system lev...

Page 3: ...ESSORS 2 volume set MEMORY PRODUCTS MICROCOMPUTER PRODUCTS MICROPROCESSORS 2 volume set MOBILE COMPUTER PRODUCTS i750 i860 i960 PROCESSORS AND RELATED PRODUCTS PACKAGING PERIPHERAL COMPONENTS PRODUCT...

Page 4: ...um Processor User s Manual consists of three books Pentium Processor Data Book Order Number 241428 the 82496 Cache Controller and 82491 Cache SRAM Data Book Order Number 241429 and the Architecture an...

Page 5: ...Intel487 Intel intel inside Intellec iPSC iRMX iSBC iSBXTM iWARpTM LANDeskTM LANPrint LANProtect LANSelect LANShell LANSight LANSpace LANSpool MAPNEFM Matched MCS Media Mail NetPort NetSentry NetSigh...

Page 6: ...96 Cache Controller and multiple 82491 Cache SRAMs combine with the Pentium processor to form a CPU Cache chip set designed for high performance servers and function rich desktops The high speed inter...

Page 7: ......

Page 8: ...1 SYNCHRONOUS SNOOP MODE 2 6 2 3 2 2 CLOCKED ASYNCHRONOUS SNOOP MODE 2 6 2 3 2 3 STROBED SNOOP MODE 2 6 2 3 3 Memory Bus Modes 2 6 2 3 3 1 CLOCKED MEMORY BUS MODE 2 7 2 3 3 2 STROBED MEMORY BUS MODE 2...

Page 9: ...and Back Invalidation Cycles 3 18 3 8 3 Write Once Policy 3 19 3 8 4 MESI State Tables Pentium Processor CPU Cache Chip Set State Changes 3 19 CHAPTER 4 CACHE INITIALIZATION AND CONFIGURATION 4 1 CONF...

Page 10: ...ddress Integrity 5 22 5 1 3 1 CPU BUS ADDRESS PARITY 5 22 5 1 3 2 MEMORY BUS ADDRESS PARITY 5 22 5 1 4 Data Control 5 23 5 1 4 1 CPU DATA BUS TRANSFER CONTROL 5 24 5 1 5 Memory Bus Mode Selection 5 24...

Page 11: ...5 36 CYCLE CONTROL SIGNALS 5 36 MEMORY ADDRESS BUS AND ADDRESS CONTROL SIGNALS 5 37 MEMORY DATA BUS AND DATA CONTROL SIGNALS 5 37 CACHE SYNCHRONIZATION SIGNALS 5 37 CPU SiGNALS 5 37 TEST SIGNALS 5 37...

Page 12: ...88 5 2 2 89 5 2 2 90 I CONTENTS Page CPCD 5 80 CPWT 5 81 CRDY 5 82 CSCYC 5 84 CW R 5 85 CWAY 5 86 D C 5 87 D 63 0 5 88 DP 7 0 5 89 DRCTM 5 90 EADS 5 92 EWBE 5 93 FERR 5 94 FLUSH 5 95 FRCMC 5 97 FSIOUT...

Page 13: ...2 2 138 5 2 2 139 5 2 2 140 5 2 2 141 5 2 2 142 5 2 2 143 x Page MOOE 5 148 MEOC 5 149 MFRZ 5 151 MHITM 5 153 MISTB 5 154 MKEN 5 155 MOCLK 5 156 MOSTB 5 158 MRO 5 159 MSEL 5 161 MSTBM 5 163 MTHIT 5 1...

Page 14: ...TATE SYNCHRONOUS SNOOP MODE 6 18 6 5 I O CyCLES 6 21 CHAPTER 7 ELECTRICAL SPECIFICATIONS 7 1 POWER AND GROUND 7 1 7 2 DECOUPLING RECOMMENDATIONS 7 1 7 3 CONNECTION SPECIFICATIONS 7 1 7 4 MAXIMUM RATIN...

Page 15: ...CAN REGISTER CELL 11 13 11 2 6 Boundary Scan Description Language BSDL 11 13 11 2 7 Boundary Scan Signal Descriptions 11 13 11 3 82491 CACHE SRAM TESTING 11 13 APPENDIX A SUPPLEMENTAL INFORMATION Figu...

Page 16: ...ium Processor 82491 Cache SRAM Data Parity Connections 5 29 512K Cache 64 Bit Bus 5 31 BLEC Deassertion Due to ADS Assertion 5 52 BLEC Assertion Due to CNA or CRDY Assertion 5 53 BLEC Assertion Due to...

Page 17: ...1 15 Pentium Processor 82496 Cache Controller Interface Signals 1 15 Pentium Processor 82491 Cache SRAM Interface Signals 1 15 82496 Cache Controller 82491 Cache SRAM Interface Signals 1 16 Pentium P...

Page 18: ...Purpose and the New Parameters 7 5 Description of Maximum Flight Time and Clock Skew 7 8 Signal Group CPU to Cache RAM CPU CRAM 66 MHz 256 Kbyte Version 7 9 Signal Group CPU to Cache CPU Cache 66 MHz...

Page 19: ...put External Interface Buffer Model Parameters 8 6 Diode Parameter List 8 8 Data for Diode I V Curves 8 9 CPU Cache Chip Set Package Information Summary 9 1 Pentium Processor Mechanical Specificatons...

Page 20: ...1 Pinouts I...

Page 21: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 22: ...as W RM ADSC N 000 0 Vee Vss AP ADSI P 0 000 Vee Vas HLDA BEl Q 0 000 Vee VBS PCHK seve ROOOO Vee Vas PWT BESt 5 0 000 PENTIUM TM PROCESSOR PINOUT TOP VIEW D46 DP6 D54 DP7 OOOOE 051 D49 D57 Vee OOOOF...

Page 23: ...0 F 07 05 Vas Vee 0000 G OPO FERRI Vas Vee 0000 H CACHE KEN IU Vas 0000 BOFF NAI Vas Vas 000 0 K BROYNBRDVClAHOlD Vss o 0 0 0 L HITM EAOS WBfWT Vas 0000 M ADSC WIRI Vas Vee o 0 0 0 N ADSt AP Vss Vee...

Page 24: ...000 9 MST3 Vee Yss MTAG2 MTAG1 SET7 Vcc SET9 SET10 BT3 10 0 0 0 0 0 82496 CACHE CONTROLLER PINOUT TOP VIEW o 0 0 0 0 10 Vss Vcc Vss MTAGO MSETB SET8 Vss Vss Voo Vas 11 00000 0000011 MST2 Vee Vss MSET1...

Page 25: ...rna SET9 V sm 82496 Mf MfA V V MBT l 0 0 0 0 0 CACHE 0 0 0 0 0 10 CONTROLLER 10 V Vee V Vn SETa PINOUT MSET8 MTAGO v Vee v BOTTOM VIEW 11 0 0 0 0 0 0 0 0 0 0 11 B Veo v SETS ClK MSET2 MSET10 Vss Vee M...

Page 26: ...DATA6 Vee Vee 82491 CDATA3 MDATA2 CACHE CDATAl SRAM V PINOUT Vas MDATAS TOP VIEW CDATA6 Vee CDATAS MDATAl Vee Vss CDATA2 MDATA4 CDATAO Vee Vss MDATAO CDATA4 V WAY MDOE WRARR MZBT CRDY i S 5 Iii i cc I...

Page 27: ...A6 82481 CDATA3 CACHE Vee SRAM CDATAI PINOUT MDATA2 BOTTOM VIEW Vss VII CDATA6 MDATA5 CDATA5 Vee Vee MDATAI CDATA2 VII CDATAO MDATA4 Vss Vee CDATA4 MDATAO WAY Vas WRARR MooEl CRDY MZBT r m c I m Iii i...

Page 28: ...11 T14 08 F04 040 014 BE2 U06 INIT T20 A12 U14 09 C12 041 B19 BE3 V01 INTR N18 A13 T13 010 C13 042 020 BE4 T06 INV A01 A14 U13 011 E05 043 A20 BE5 504 IU J02 A15 T12 012 C14 044 021 BE6 U07 IV B01 A16...

Page 29: ...T04 BT1 W21 031 C10 063 H18 OP7 E21 TOI T21 BT2 T07 EAOS M03 TOO S21 BT3 W20 EWBE A03 TMS P19 FERR H03 TRST S18 FLUSH U02 W R N03 WB WT M02 VCC VSS A04 C01 N21 W08 B05 B15 H02 L20 020 V10 A05 001 POi...

Page 30: ...ACHE 003 SNPSTB S04 BLE 017 O C J15 MCYC 018 SWENO R02 BLEC P19 ORCTM N02 MHITM J05 SYNC R05 BOFF H16 EAOS K16 MKEN S02 TCK 004 BROY 002 EWBE T03 MRO K02 TOI P04 BROYC1 E16 FLUSH P05 MTHIT H04 TOO 005...

Page 31: ...08 SET7 E10 TAG7 B03 BTO A16 SET8 E11 TAG8 E08 BT1 A14 SET9 C10 TAG9 B02 BT2 A12 SET10 B10 TAG10 CO2 BT3 A10 TAG11 006 Memory Bus Address MCFAO R17 MSETO R16 MTAGO R11 MCFA1 P15 MSET1 013 MTAG1 010 MC...

Page 32: ...G18 819 A11 J03 809 B01 H02 T06 A15 J17 810 B06 H18 T07 A18 J19 811 B07 H19 T08 A19 K03 812 B08 J02 T09 C01 K05 813 B09 J18 T10 C06 K17 814 B11 K15 T11 C07 L03 T01 B12 K19 T12 C08 L05 T19 B13 L01 T13...

Page 33: ...O 18 HITM 62 W R 58 A11 78 MDATA1 14 MAWEA 41 WAY 45 A12 79 MDATA2 10 MBE 32 WBA 38 A13 80 MDATA3 6 MBRDY 22 WBTYP 37 A14 81 MDATA4 16 MClK 26 WBWE 39 A15 82 MDATA5 12 MCYC 42 WRARR 44 MDATA6 8 MDOE 2...

Page 34: ...e internal pull up or pull down resistors and are glitch free Table 1 14 lists the interconnects between the optimized interface signals Tables 1 15 to 1 18 list pin states at reset Output pins Input...

Page 35: ...n Table Cross Reference In the following tables a signal name in brackets represents a configuration input signal sampled at RESET and a signal name in parenthesis represents a strobed mode signal Tab...

Page 36: ...MCFA 6 0 MSET 10 0 MTAG 11 0 Table 1 6 82491 Cache SRAM MBC Interface Signals BRDY MBRDV MISTB MEOC MZBT MX4 8 TDO CLK MCLK MSTBM MFRZ MDLDRV RESET TMS CRDY MDATA 7 0 MOCLK MOSTB TCK MBE PAR MDOE MSE...

Page 37: ...I CC Address Strobe signal from the Pentium processor to the 82491 Cache I CS SRAMs ADS indicates the start of a new valid CPU bus cycle and is 0 P functionally identical to ADSC The 82496 Cache Cont...

Page 38: ...Guaranteed Transfer is generated by the Memory Bus Controller MBC to indicate that it is committed to completing a given memory bus cycle Until BGT is active the 82496 Cache Controller owns the cycle...

Page 39: ...sor BRDYC input during cache hit and posted cycles BRDYC2 0 CC Burst Ready Cache 2 is output by the 82496 Cache Controller to the 82491 Cache SRAM BRDYC input during cache hit and posted cycles BREQ 0...

Page 40: ...memory bus cycle needs data or code CDATA 7 0 I O CS Cache Data I O pins are the 8 bits comprising the I O data bus interface between each 82491 Cache SRAM and the Pentium processor data bus When a 8...

Page 41: ...ocessor PCD attribute to give the memory bus controller direct access CPCD is valid with CADS and SNPADS CPWT 0 CC 82496 Cache Controller Page Write Through is a latched version of the Pentium process...

Page 42: ...E state and move a line directly to the M state DRCTM allows the chip set to support read for ownership and cache to cache transfers without main memory update and is sampled when SWEND is asserted E...

Page 43: ...active along with SLFTST the High Impedance Output Configuration signal causes the 82496 Cache Controller to float all output pins HIGHZ shares a pin with the 82496 Cache Controller input signal MBAL...

Page 44: ...rocessor will execute the instruction in spite of the pending exception When the CRO NE bit is zero IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating point ins...

Page 45: ...during which cacheability is determined has expired When KWEND is as serted the 82496 Cache Controller latches the memory cacheability signal MKEN and the Memory Read Only Signal MRO and makes determ...

Page 46: ...enabled only while MAOE is inactive MAP 1 0 CC Memory Address Parity is an input when MAOE 1 Snoop cycle and indicates the address parity of the line address bits MAP is an Output when MAOE O 82496 Ca...

Page 47: ...next data upon the rising edge of MCLK or MOCLK for writes if applicable MBRDY is qualified by MSEL MBRDY shares a pin with the 82491 Cache SRAM input signal MISTB MBT 3 0 0 CC The Memory Branch Trac...

Page 48: ...e tri stated When MDOE is active low the MDATA pins drive data Because it is unrelated to ClK and MClK MDOE functions the same during strobed and clocked memory bus operations MEOC I CS Memory End of...

Page 49: ...is READ ONLY For the Pentium processor READ ONLY code lines are cacheable in the first level cache Read Only data lines are not cacheable in the first level cache READ ONLY lines are cached in the 824...

Page 50: ...O pins to be used for the memory bus If MX4 8 is HIGH four I O pins are used If MX4 8 is lOW eight I O pins are used MX4 8 shares a pin with the 82491 Cache SRAM input signal MZBT MZBT I CS When sampl...

Page 51: ...ddition the machine check enable bit in CR4 is set to 1 the Pentium processor will vector to the machine check exception before the beginning of the next instruction PRDY 0 P The PRDY output pin indic...

Page 52: ...he Controller s memory address bus driving strength SNPCLK SNPMD Indicates whether the snoop mode is synchronous clocked or strobed MALE WWOR Enforces strong or weak write ordering consistency CRDY SL...

Page 53: ...ESET while MBALE is HIGH active 82496 Cache Controller self test is invoked SLFTST shares a pin with the 82496 Cache Controller input signal CRDY SMI I P The System Management Interrupt causes a syste...

Page 54: ...ted to the snoop clock source SNPMD shares a pin with the 82496 Cache Controller input signal SNPClK SNPNCA I CC Snoop Non Caching Device Access is sampled with SNPSTB and indicates to the 82496 Cache...

Page 55: ...2496 Cache Controller I P or 82491 Cache SRAM components on the TOI input pin on the rising edge of TCK when the TAP controller is in an appropriate state TDO 0 CC The Test Data Output is a serial out...

Page 56: ...WBTYP shares a pin with the Optimized Interface Configuration signal LRO WBWE 0 CC The 82496 Cache Controller Write Back Buffer Write Enable pin is used I CS in conjunction with the WBA and WBTYP pins...

Page 57: ...OK ohms Table 1 12 Pentium Processor CPU Cache Chip Set Internal Pull Down Resistors Pentium Processor 82496 Cache Controller 82491 Cache SRAM none none BLEC Table 1 13 Pentium Processor CPU Cache Chi...

Page 58: ...6 A5 A4 A 16 7 SET 10 1 SET 9 0 A 15 6 A 14 5 A17 TAGO SET10 A15 A 28 18 TAG 11 1 TAG 10 0 A29 CFA2 TAG 11 A30 CFA3 CFA2 A31 CFA4 CFA3 ADS 0 ADS I ADSC O ADS I AHOLD I AHOLD 0 AP 1 0 AP 110 BE 7 0 0 B...

Page 59: ...0 PWT I SCYC 0 SCYC I W R 0 W R I W R I WAY 0 WAY I WBIWT I WBIWT O WBA SEC2 0 WBA SEC2 I WBTYP LRO 0 WBTYP LRO I WBWE LR1 0 WBWE LR1 I WRARR 0 WRARR I The Pentium processor Byte Enable outputs are co...

Page 60: ...roller High CM IO 82496 Cache Controller Undefined NENE 82496 Cache Controller Undefined CPCD 82496 Cache Controller Undefined PALLC 82496 Cache Controller Undefined CPWT 82496 Cache Controller Undefi...

Page 61: ...ntroller low Synchronous to ClK BP 3 2 Pentium processor Synchronous to ClK PM BP 1 0 BRDYC1 82496 Cache Controller low Synchronous to ClK BRDYC2 82496 Cache Controller low Synchronous to ClK BREQ Pen...

Page 62: ...rocessor low Synchronous to ClK INV 82496 Cache Controller High Synchronous to ClK IPR 82496 Cache Controller low Synchronous to ClK IU Pentium processor High Synchronous to ClK IV Pentium processor H...

Page 63: ...or High Synchronous to ClK Bus Hold BOFF SMIACT Pentium processor low Asynchronous SMlN 82496 Cache Controller low Synchronous to ClK SNPADS 82496 Cache Controller low Synchronous to ClK SNPBSY 82496...

Page 64: ...ous to ClK 82491 Cache SRAM BRDY Pentium processor low Synchronous to ClK 82496 Cache Controller 82491 Cache SRAM BRDYC Pentium processor Low Synchronous to ClK 82491 Cache SRAM BT 3 0 82496 Cache Con...

Page 65: ...Cache Controller low Synchronous to ClK M IO 82496 Cache Controller Synchronous to ClK MALE WWOR 82496 Cache Controller High low Asynchronous Synchronous to ClK MAOE 82496 Cache Controller low Asynch...

Page 66: ...ronous to ClK PWT 82496 Cache Controller High Synchronous to ClK PEN Pentium processor low Synchronous to ClK RIS Pentium processor Asynchronous RESET Pentium processor High Asynchronous 82496 Cache C...

Page 67: ...nchronous to ClK WBTYP LRO 82491 Cache SRAM I Synchronous to ClK WBWE lR1 82491 Cache SRAM low Synchronous to ClK WRARR 82491 Cache SRAM low Synchronous to ClK NOTES 1 DRCTM and MWB WT must be synchro...

Page 68: ...che SRAM Note 2 RESET BOFF MDOE inactive NOTES 1 When inputs Synchronous to ClK SNPClK or SNPSTB When outputs Synchronous to ClK MAOE active and MALE high 2 Synchronous to ClK MClK MOClK or Asynchrono...

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Page 70: ...Cache Architecture Overview I 2...

Page 71: ......

Page 72: ...ve 64 and 128 bits are selectable configurations The 82496 Cache Controller is a high performance write back write through cache controller providing integrated tags and comparators and implementing t...

Page 73: ...on MRU hit One wait state read hit on MRU misses Zero wait state write hit cycles Concurrent CPU and Memory Bus transactions Support of synchronous asynchronous and strobed memory bus architectures Su...

Page 74: ...che Controller Block Diagram 82491 Cache SRAMs COB6 CONTROL TO 824910 82491 Cache SRAMs are used to implement cache SRAM storage and data path The 82491 Cache SRAM contains latches multiplexers and gl...

Page 75: ...e 2 3 The MBC works with the 82496 Cache Controller to perform all operations which reach the memory bus including line fills including allocations and write backs System designers can optimize their...

Page 76: ...ler 82491 Cache SRAM physically line size sectoring etc what snooping mode to use and which memory bus mode is optimal Configurations are selected by altering the 82496 Cache Controller 82491 Cache SR...

Page 77: ...on the next CLK edge if resources are available The snoop response is given on the CLK edge after the snoop is performed This is the fastest possible method of snooping 2 3 2 2 CLOCKED ASYNCHRONOUS SN...

Page 78: ...erformance The signals contained within this interface are not specified with setup hold and valid delay times Intel provides layouts and flight time specifications for these signals These flight time...

Page 79: ...ller 82491 Cache SRAM is a very flexible chipset The MBC determines exactly how the 82496 Cache Controller 82491 Cache SRAM will work in a system An MBC consists of a few basic blocks a snoop logic bl...

Page 80: ...driven onto the memory bus It also performs address parity calculation and checking if desired Data path control logic controls how data is written from or read into the 82491 Cache SRAM and CPU It h...

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Page 82: ...intel Component Operation I 3...

Page 83: ......

Page 84: ...cache tag contains a memory location which is unaltered from main memory Invalid indicates that the tag is empty The 82496 Cache Controller 82491 Cache SRAM can be implemented as a write through cache...

Page 85: ...escription that follows applies to memory read and write cycles only I O and special cycles bypass the cache altogether The 82496 Cache Controller 82491 Cache SRAM follows the MESI protocol which is u...

Page 86: ...from internal operations Another category deals with MESI state changes resulting from actions by external devices Figure 3 1 diagrams a portion of the MESI coherency protocol The diagram shows state...

Page 87: ...t State Action New State Memory Bus Activity read M none M write M none snoop E S I write back read E none E write M none snoop E S I none read S none S write M E S write through snoop S I none read M...

Page 88: ...QUIRE SNOOP P51F 1M STATE LOCK DRCTM MRO SYNC FLUSH NOT SHOWN I BEFORE THE TERM MEANS INACTIVE Figure 3 1 State Changes SNOOP IINV NCA READ HIT CDB5 3 5 1 MESI State Changes Resulting From CPU Bus Ope...

Page 89: ...n the E state prior to the write it changes to the M state If the line is in the M state prior to the write it maintains that state If the line is in the S state prior to the write the cache controlle...

Page 90: ...nvalidating data in other caches in the case of write cycles 3 Sharing data between caches How the slave enacts MESI state changes following a snoop hit depends on the SNPINV and SNPNCA input attribut...

Page 91: ...opriately The memory bus controller implements line by line cacheability by asserting the MKEN signal The Page Caching Disabled attribute is driven by the processor s PCD output and corresponds to a c...

Page 92: ...491 Cache SRAM already has an exclusive or modified copy of the line PWT has no effect on the cycle 3 6 3 Read Only Accesses MRO The Memory Read Only input MRO is driven by the memory bus to indicate...

Page 93: ...erted during main memory reads for special 82496 Cache Controller 82491 Cache SRAM data accesses including allocation read for ownership and cache to cache transfer without main memory update 3 7 STAT...

Page 94: ...he Controller is allowed to go into exclusive states E M DRCTM Memory Bus Direct To M indication DRCTM input pin When active forces the line state to bypas E and go to M provided MWT MKEN Memory Bus C...

Page 95: ...r generates a writeback cycle when MODIFIED data cached in the 82496 Cache Controller needs to be copied back into main memory A write back cycle affects a complete 82496 Cache Controller line WTHR 82...

Page 96: ...96 Cache Controller for non cacheable accesses SRUP 82491 Cache SRAM SRAM update This cycle occurs any time new information is placed in the 82491 Cache SRAM cache An SRAM update is implied in the LFI...

Page 97: ...aching in L1 code cache LOCK S RTHR KEN Read Through Cycle Data from Memory I PCD MKEN LOCK I RNRM KEN Non Cacheable Read Locked cy cles PCD MKEN LOCK MRO DAT S LFIL KEN Cacheable data read Read Only...

Page 98: ...ot Read Only No write through E cycle no lock request Allow going into exclusive state TRO IPWT LOCK IMWT DRCTM WTHR SRUP Not Read Only No write through M cycle no lock request allow going into exclus...

Page 99: ...only indicate MTHIT stay exclusive S S MTHIT I I Table 3 5 Snooping 82496 Cache Controller with Invalidation Request Pres Memory Bus CPU Bus State Next State Activity Activity Comments M I MTHIT INOR...

Page 100: ...e SRAM secondary cache See Figure 3 2 This means that the Pentium processor caches are guaranteed to be a subset of the 82496 Cache Controller 82491 Cache SRAM Inclusion is the property which explains...

Page 101: ...to drive the snooping address It then drives EADS to indicate that the address is valid and should be strobed for the snoop The Pentium processor will respond to the snoop with the HIT and HITM signa...

Page 102: ...Pentium processor by executing an inquire cycle Read only lines are treated as valid and invalid only Neither the 82496 Cache Controller nor the Pentium processor will cache read only lines in an excl...

Page 103: ...E LFIL M NO 1 0 M None 3 I 0 0 0 S LFIL M NO 1 0 M None 3 4 5 S x x x S None E I x x 1 I Read E I x x 0 S LFIL E S x x x S None S I x x 1 I Read S I x 1 0 I Read S I x 1 0 S LFIL S I x 0 0 S LFIL S I...

Page 104: ...Controller 82491 Cache SRAM Caches To Cache P D C W I A T C C Initial Initial H Final CPU State Cycle State E State Bus of Type of CPU of CPU Activity Cache Locked I x x 1 I WT X Not M x x x M None M...

Page 105: ...r SNOOP Cycles 82496 Cache Controller 82491 Cache SRAM to CPU Caches To From Mem CPU Bus I S S N N N N V P P 0 Initial Final Initial N I Final Memor t State of State of CPU Bus State of C N State of y...

Page 106: ...6 Cache Controller 82491 Cache SRAM SWB Snoop Write Back INQR Inquire 82496 Cache Controller snoops the Pentium processor BINV Back Invalidate COMPONENT OPERATION Refer to Table 3 4 and Table 3 5 for...

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Page 108: ...Cache Initialization and Configuration I 4...

Page 109: ......

Page 110: ...alance between performance and memory bus controller design complexity and cost Figure 4 1 summarizes the basic configurations available when using the 82496 Cache Controller 82491 Cache SRAM with the...

Page 111: ...alling edge of RESET refer to Figure 4 2 The configuration inputs must meet the following timing requirements with respect to RESET 1 The configuration inputs must meet setup and hold times with respe...

Page 112: ...e MBC for at least 4 clocks prior to the falling edge of RESET BUSCHK configures part of the Pentium processor address and control bus for one of two buffer sizes 2 BRDYC is driven low to the Pentium...

Page 113: ...BGT signal During reset the CLDRV pin should be driven low or high as shown in Table 4 7 During normal operation this pin acts as the BGT signal and should be driven accordingly 4 2 PHYSICAL CACHE Th...

Page 114: ...rmine the number of inquires and back invalidations to the CPU 4 2 3 TagRAM Size The 82496 Cache Controller 82491 Cache SRAM tagRAM size can be configured with 4K or 8K tag entries By reducing tagRAM...

Page 115: ...with 14 bits per tag A read only bit and two state bits are stored with each tag in the tag array of the 82496 Cache Controller The read only bit provides compatibility with certain shadow ROM techni...

Page 116: ...g TAG SET Number CFA6 CFA5 CFA4 CFA3 CFA2 CFA 1 0 11 0 10 0 1 A5 S VSS A31 T A30 T A29 T A 4 3 CS A 28 17 A 16 6 2 A5 CL VSS A31 T A30 T A29 T A 4 3 CS A 28 17 A 16 6 3 A6 S A5 L VSS A31 T A30 T A 4 3...

Page 117: ...B MCFA3 MCFA2 MTAG11 MTAGO MSET10 MCFA6 MCFA5 MCFA4 MSETO MCFA1 MCFAO TAG SET LINE SUBLINE In l 1 1 I I SUBLINE MBALE LINE ADDRESS LATCH ADDRESS LATCH MAOE MBAOE 1 1 1 l l MCFA MTAG MCFA MSET MCFA MCF...

Page 118: ...e SRAM may be designated as a parity device by driving the MBE PAR pin low during reset In parity configuration CDATA 3 0 are used to store 4 parity bits and CDATA 7 4 are used as 4 bit enables The fo...

Page 119: ...iguration input MDLDRV is used to select the buffer Refer to Table 7 26 for the buffer selection specifications and the appropriate value of MDLDRV CLDRV selects the driving strength of the 82496 Cach...

Page 120: ...s MCLK CLK This selection provides an asynchronous memory bus MCLK may be any frequency that optimizes the memory bus Synchronization is required to interface memory bus and cycle control signals 4 3...

Page 121: ...nected to the SNPCLK pin The 82496 Cache Controller will automatically detect the clock and enter Clocked Snooping Mode 4 3 3 Strong Weak Write Ordering 4 3 3 1 DESCRIPTION A system which maintains st...

Page 122: ...section 5 1 10 for a description and the memory bus controller rules which will allow the 82496 Cache Controller to operate in strong write ordered mode without coherency problems 4 3 3 2 CONFIGURATI...

Page 123: ......

Page 124: ...5 Hardware Interface I...

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Page 126: ...ess by signalling these caches to snoop If another cache signals that it contains modified data the MBC permits that cache to write out the modified data before it completes the cycle Once transfers h...

Page 127: ...the E and M states and unlocked read hits to S state independently of the MBC and the system All other cycles require access to memory bus arbitrated by the MBC Cycles on the memory bus are requested...

Page 128: ...ontroller If a snoop hits a modified location before BGT of that cycle the 82496 Cache Controller aborts the request and generates a snoop write back cycle which writes back the modified data Followin...

Page 129: ...requests from other bus masters SWEND indicates to the MBC that data transfers may begin The MBC may begin transfers early anticipating that no other cache has modified data If another cache does need...

Page 130: ...4 processor Cacheable Read Cache Line Controller Line Pentium Processor CPU Cache Chip Set 0 0 0 1 0 0 x 82496 4 processor Cacheable Read Cache Line Controller Line 82496 Cache Controller 82491 Cache...

Page 131: ...2496 Cache Controller 82491 Cache SRAM the 82496 Cache Controller asserts the MCACHE pin to the MBC During the cycle the MBC returns MKEN active to render the line cacheable Because the needed informa...

Page 132: ...cle The data is written to memory and all other caches are snooped to invalidate copies of the altered line If the line is not marked read only and PWT is not active it may be upgraded to E or M state...

Page 133: ...96 Cache Controller responds with the MHITM signal asserted and then drives the SNPADS signal SNPADS is provided because the MBC must receive indication that a snoop write back must be serviced immedi...

Page 134: ...ory the caches mark their copies of the data as shared For the supplying cache this designation is done automatically when the cache is snooped by another cache For the receiving cache the designation...

Page 135: ...operations For optimum performance issue FLUSH to only the 82496 Cache Controller SYNC will cause both the 82496 Cache Controller 82491 Cache SRAM and Pentium processor caches to write back all modif...

Page 136: ...96 Cache Controller samples for the snoop address SNPINV SNPNCA MBAOE MAOE and MAP If MAOE is active the 82496 Cache Controller is driving the bus and cannot perform a snoop In this scenario all other...

Page 137: ...ure 5 5 shows the clocked asynchronous snooping mode In clocked snooping mode the snoop address address parity and snoop parameters are sampled with the rising edge of SNPCLK in which SNPSTB is sample...

Page 138: ...INTERFACE CDB34 In strobed snooping mode Figure 5 6 no clocks are needed to initiate the snoop The snoop address address parity and snoop parameters are sampled with the falling edge of SNPSTB and the...

Page 139: ...strobed mode is selected If SNPMD is connected to an external clock clocked mode is selected and the external clock becomes the external snooping clock source 5 1 2 2 SNOOP OPERATION A snoop operatio...

Page 140: ...her snoop request As a result snoops may be pipelined Figures 5 8 and 5 9 show the fastest synchronous and asynchronous snooping possible Note that the MBC must not assert SNPSTB for a new snoop opera...

Page 141: ...I MI I 3S X I 7 I I IWI I I I I I Figure 5 8 Fastest Synchronous Snooping I Q U I I I I I I WI I 7 I WI i i 1 I IWI Figure 5 9 Fastest Asynchronous Snooping I STATE E S STATE MSTATE SNPSTB SNPINV A 0...

Page 142: ...igure 5 12 Snoop Response During Cycles Figure 5 12 shows the regions into which a snoop cycle can be partitioned Region 1 is after one memory cycle ends after CRDY and before a new cycle begins befor...

Page 143: ...Controller recognizes the BGT signal it blocks all snoops until after SWEND If SNPCYC has not been issued before BGT is asserted the snoop is blocked ClK BGT SWEND orCRDY Ix_ __ L S No O c Bl O_ C E...

Page 144: ...t not allow snoops to occur This section describes these cases The 82496 Cache Controller allows the memory bus controller to pipeline snoop operations A second snoop request and snoop address can be...

Page 145: ...is surrounded by the modified data from cache 2 The resulting line is the most recently modified line Note that the line in cache 2 is invalidated before the cache to cache transfer Also once the tra...

Page 146: ...gners must be able to determine both of the physical addresses which the locked sequence will read and write If both addresses are known snoops may be allowed to any other address Snoops are not allow...

Page 147: ...ress pins A 31 5 and drives that value on the AP pin Refer to the Pentium Processor Data Book for more details Note that the 82496 Cache Controller does not internally store the address parity bit it...

Page 148: ...ither from two CLKs after SNPSTB synchronous snoop mode or one CLK after SNPCYC clocked and strobed snoop modes until that same time during the subsequent snoop operation MAPERR is driven with the tim...

Page 149: ...e it is a requirement that the MBC provide the Pentium processor 82496 Cache Controller cache controller and all 82491 Cache SRAMs with the same BRDY input The 82496 Cache Controller also provides the...

Page 150: ...T MSEL and MFRZ see the detailed pin descriptions for how these signals are sampled Strobed mode signals have set up and hold times to asynchronous control signal transitions To place the 82491 Cache...

Page 151: ...91 Cache SRAM uses the buffers in an alternating fashion using the buffer available when the other has a posted write or is being used for a memory read During allocation cycles read for ownership may...

Page 152: ...is asserted the 82491 Cache SRAM discards the buffer contents used in the current cycle and on line fills and allocations loads the data into the 82491 Cache SRAM cache SRAM array CRDY must be asserte...

Page 153: ...FER 0 OR 1 CDB40 A 82491 Cache SRAM may be designated as a parity device This is done be strapping the MBE PAR pin low during RESET Two 82491 Cache SRAM SRAMs are used to provide the memory bus contro...

Page 154: ...Such a scheme will require synchronization Some system designers will choose a divided synchronous memory bus wherein the memory system runs at 33 MHz and synchronization is unnecessary The following...

Page 155: ...d control For a clocked memory bus implementation a description of a 512K cache connection to a 64 bit memory bus follows The 82491 Cache MDOE input is divided into two signals MDOEL and MDOEH Similar...

Page 156: ...s for a Pentium processor CPU Cache Chip Set subsystem This section describes these signal relationships enforced by the 82496 Cache Controller and 82491 Cache SRAM and those which the MBC must enforc...

Page 157: ...le BGT KWEND SWEND 6 Cycles initiated by SNPADS require CRDY but do not require other cycle progress signals BGT KWEND SWEND 5 1 12 82496 Cache Controller Input Signal Recognition Requirements 1 CNA i...

Page 158: ...tive 5 1 15 Pentium Processor 82496 Cache Controller and 82491 Cache SRAM BROY Requirements 1 The first BRDY must be asserted with or following BGT BRDY BGT 2 The first BRDY must be after CDTS BRDY CD...

Page 159: ...ills allocations write through potentially upgradeables NOTE SWEND has an additional function of enabling snoops If SWEND is not activated for a cycle snoops will be disabled until CRDY of the cycle 4...

Page 160: ...e mutual exclusion of processor access to shared data special care is needed to insure that once the semaphore has been obtained that all back invalidations of the primary Cache have been completed Th...

Page 161: ...ge and its operational mode The When Sampled When Driven section indicates when the signal is generated or sampled The Relation to Other Signals section discusses how other signals are related to the...

Page 162: ...BUSCHK CLK FERR FLUSH Pentium processor FRCMC HIT HLDA HOLD IBT IERR IGNNE INIT INTR IU IV NMI PCHK PEN PRDY RlS RESET SM SMIACT 5 2 1 9 TEST SIGNALS TCK TDI IDO TMS TRST 5 2 1 10 PENTIUM PROCESSOR BU...

Page 163: ...Input 82491 Cache SRAM signals pins 82 81 80 79 78 77 76 75 73 71 70 69 68 67 66 65 Synchronous to ClK Signal Description Refer to the Pentium Processor Data Book for a detailed description of the CP...

Page 164: ...E 5 2 2 2 A20M A20M Address bit 20 Mask Masks address bit 20 Input to Pentium processor pin U05 Asynchronous Signal Description Refer to the Pentium Processor Data Book for a detailed description of t...

Page 165: ...ontroller pin C16 Synchronous to ClK 82496 Cache Controller and 82491 Cache SRAM internal Pull ups Signal Description Refer to the Pentium Processor Data Book for a detailed description of this signal...

Page 166: ...oller Output from Pentium processor pin N04 Synchronous to ClK Signal Description This signal is functionally identical to the Pentium processor ADS output signal and is connected to the 82496 Cache C...

Page 167: ...to perform CPU inquire back invalidation flush or sync cycles When AHOLD is active the CPU does not drive the CPU address bus During address hold the 82496 Cache Controller will drive the address bus...

Page 168: ...ring processor snoop flush or sync cycles For processor initiated cycles AP is valid from ADS to NA or BRDY For processor snoop cycles the 82496 Cache Controller drives AP valid during the CLK of EADS...

Page 169: ...us Indicates a CPU address bus parity error during inquire or back invalidation cycles Output from Pentium processor pin W03 Synchronous to ClK Glitch Free Signal Description Refer to the Pentium Proc...

Page 170: ...tive for a minimum of one CPU CLK The 82496 Cache Controller begins checking address parity on the clock of the CPU ADS and will keep checking until the address is internally latched This internal lat...

Page 171: ...ller for 32 bit high performance operating systems It has features built in which improve performance in multitasking operating systems both uniprocessor and multiprocessor It meets the functional req...

Page 172: ...ium Processor Data Book for a detailed description of the BE 7 0 signals For a 512K cache configuration 16 82491 Cache SRAM devices each BE 7 0 output of the Pentium processor is connected to the BE i...

Page 173: ...form snoop lookups until the end of the snooping window until SWEND is active A snoop address is latched if SNPSTB is asserted between BGT and SWEND but the snoop lookup does not begin until the secon...

Page 174: ...nly if neither SNPCYC nor SNPBSY and MHITM are active If SNPBSY is active BGT is only blocked in hits to M cases where the bus would be writing back the modified data KWEND BGT must be asserted before...

Page 175: ...gth information from the Pentium processor CACHE and D C pins and from the MKEN and MRO inputs from the MBC It will drive BLAST as an output to provide the burst last indication to the 82491 Cache SRA...

Page 176: ...al is not necessary when using the Pentium processor with the 82496 Cache Controller 82491 Cache SRAM cache since those signals are latched within the 82496 Cache Controller and 82491 Cache SRAM and a...

Page 177: ...enable latching is controlled by a 82491 Cache SRAM input BLEC from the 82496 Cache Controller The latch samples BE at each clock rising edge when BLEC is low When BLEC is high the latch is closed an...

Page 178: ...CRDY Assertion If the ADS cycle to the 82496 Cache Controller is a cache hit then BLEC will be asserted immediately i e it could be inactive for as short as one CLK as shown or longer See Figure 5 25...

Page 179: ...2496 Cache Controller inquire cycle deadlock on usage of the CPU bus BOFF when asserted allows the 82496 Cache Controller to prevent CPU bus deadlock by causing the Pentium processor to abort the curr...

Page 180: ...16 BP 3 2 PM BP 1 0 BP 3 2 PM BP 1 0 Breakpoint and Performance Monitoring BP 3 0 externally indicate a breakpoint match Outputs from Pentium processor Signal Description Please refer to Appendix A fo...

Page 181: ...latch burst counter to allow the next 64 bit read data slice to be available on the CPU data bus At the same time BRDY latches the previous data slice into the CPU With the exception of I O cycles BRD...

Page 182: ...Line Ratio COTS BROY must be asserted after COTS is asserted CROY On CPU read cycles the last BROY lBROY of Cycle N must be activated prior to the CROY of cycle N 1 KWENO BROY of a non cacheable 8249...

Page 183: ...2 18 BRDye BRDYC Bur st Ready Cache Data input and output control signal Input to Pentium processor pin l03 and 82491 Cache SRAM pin 61 Synchronous to ClK Signal Description See BRDYCl and BRDYC2 sign...

Page 184: ...Cache SRAM cache subsystem has either presented data to the CPU or accepted data from the CPU When Driven BRDYC1 is driven during non locked read hit cycles when data from the 82491 Cache SRAM is read...

Page 185: ...cache subsystem has either presented data to the CPU or accepted data from the CPU When Driven BRDYC2 is driven during non locked read hit cycles when data from the 82491 Cache SRAM is read on the CPU...

Page 186: ...Bus Request Indicates that the Pentium processor has generated a bus request Output from Pentium processor pin V02 Synchronous to elK Signal Description Refer to the Pentium Processor Data Book for a...

Page 187: ...oller If the BT 3 0 pins are left unconnected between the Pentium processor and the 82496 Cache Controller the MBT 3 0 outputs of the cache controller reflect a latched version of the BT 3 0 inputs du...

Page 188: ...active the 82491 Cache SRAM will set an internal mux so that CPU read data comes from the memory bus memory cycle buffers instead of the array The internal mux will stay in this condition until BRDY B...

Page 189: ...e 4 1 refer to section 4 1 1 at least 4 CPU clocks prior to the falling edge of RESET To simplify the configuration process the Pentium processor BUSCHK input can be tied to the inverse of RESET with...

Page 190: ...ndication Indicates Pentium processor internal cacheability attribute Output from Pentium processor pin J04 Input to 82496 Cache Controller pin H15 Synchronous to ClK Signal Description Refer to the P...

Page 191: ...and KLOCK are valid Every memory bus cycle is initiated by CADS or SNPADS If the 82496 Cache Controller receives a snoop request and reports a hit to a line in M state before BGT is asserted the cycl...

Page 192: ...res BGT and CRDY inputs from the MBC CDTS CADS CDTS for all write through cycles Since allocations do not require BRDY s to the CPU the CDTS of an allocation cycle will always occur with CADS of the l...

Page 193: ...when to return BRDY to the CPU for Flush and Write Back special cycles CAHOLD is used during 82496 Cache Controller self test to indicate the pass fail condition It can be sampled in the CLK after th...

Page 194: ...he Controller write back snoop write back and allocation cycles CCACHE is used by the MBC to determine the number of BRDY s to provide to the CPU See Table 5 2 Table 5 2 CCACHE Use in Determining the...

Page 195: ...and allocation During read only read miss cycles CD C helps to determine the number of BRDY s which the MBC must provide to the CPU If CD C is low the MBC must provide 4 BRDY s If CD C is high the MB...

Page 196: ...iled description of the Pentium processor D 63 0 signals When Driven Sampled CDATA 7 0 are sampled with proper valid delays in the CLK that BRDYC is driven to the Pentium processor CDATA 7 0 are drive...

Page 197: ...o indicate to the MBC that write back data is valid in the 82491 Cache SRAM write back buffer the MBC can provide the first MBRDY in the next CLK Note that MBRDY is sampled by the 82491 Cache SRAM wit...

Page 198: ...the CDTS of an allocation cycle will always occur with CADS of the linefill CADS will occur before or with CDTS CADS CDTS CNA CNA is recognized between CDTS and CRDY CDTS CNA CRDY CRDY CRDY must be af...

Page 199: ...C15 F16 B10 C10 E11 E10 E13 D12 D13 C13 D15 D14 E14 D06 C02 B02 E08 B03 D08 C04 C05 B04 E09 B05 D09 Synchronous to ClK Signal Description These configurable address pins are connected to CPU address...

Page 200: ...ector When Sampled CFG 2 0 are sampled and used as shown in the Initialization and Configuration chapter After sampling CFG 2 0 become cycle progress input signals to the 82496 Cache Controller and ar...

Page 201: ...e Controller to 82491 Cache SRAM control signals BLAST BLEC BUS MAWEA MCYC WAY WBA SEC2 WBTYP LRO WBWE LRl WRARR can be configured for one of two buffers The buffer selection is made by using the CLDR...

Page 202: ...cessor pin K18 82496 Cache Controller pin E12 and 82491 Cache SRAM pin 30 Signal Description The CLK input determines the execution rate and timing of the Pentium processor CPU Cache Chip Set Pin timi...

Page 203: ...O is high for 82496 Cache Controller initiated cycles i e 82496 Cache Controller replacement write back 82496 Cache Controller snoop write back and allocation When Driven CM lO is valid in the same CL...

Page 204: ...led beginning in the first CLK in which BGT is sampled active and until CRDY is sampled active Subsequently CNA is ignored until BGT is returned for the next cycle CNA is ignored during snoop write ba...

Page 205: ...hit to S state and write miss cycles In all cases PALLC will be inactive high See Table 5 3 Table 5 3 Using CPCD and CPWT to Determine Write Hit to 5 versus Write Miss CPCD CPWT Cycle Type 0 0 Write H...

Page 206: ...acks and allocations Write cycles with PWT active are not allocatable CPWT can be used along with CPCD to distinguish between write hit to S state and write miss cycles In all cases PALLC will be inac...

Page 207: ...next cycle For example the 82491 Cache SRAM CRDY indicates that the memory buffer in use must be emptied i e put in array or discarded CRDY also allows cycle progress signals BGT KWEND SWEND to be sa...

Page 208: ...through cycles with potential allocation PAllC 0 MBRDY For read cycles MBRDY fills the memory buffer in use CRDY empties the current memory cycle buffer read or write cycles and makes it available fo...

Page 209: ...ignal during a CPU LOCKed cycle on the memory bus CSCYC is inactive LOW during write backs snoop write backs and allocations When Driven CSCYC is valid from the CLK of CADS and SNPADS until the CLK of...

Page 210: ...signals CW R indicates whether the 82496 Cache Controller requests a read cycle or a write cycle When Driven CW R is valid with CADS and SNPADS and remains valid until CRDY or CNA is asserted Relatio...

Page 211: ...CWAY indicates the WAY which was hit During write backs CWAY indicates the WAY that was written back CWAY can be utilized by external tracking machines to maintain a set of duplicate tags that can acc...

Page 212: ...Data Code Cycle decode signal Output from Pentium processor pin V04 Input to 82496 Cache Controller pin J15 Synchronous to ClK Signal Description Refer to the Pentium Processor Data Book for a detaile...

Page 213: ...CO9 D11 D09 C11 C08 B10 A10 C07 C16 D07 C15 C06 B09 D06 D05 D1 3 D04 C14 E05 C13 C12 F04 G04 B04 G03 C04 F03 E04 E03 D03 and 82491 Cache SRAM CDATA 7 0 pins Synchronous to ClK Signal Description Refer...

Page 214: ...ATA 3 0 pins Synchronous to ClK Signal Description Refer to the Pentium Processor Data Book for a detailed description of this signal Relation to Other Signals Pin Symbol Relation to Other Signals CDA...

Page 215: ...its internally change E lines to the M state DRCTM can be used to eliminate the E state from the MESI protocol NOTE Usage of DRCTM to avoid E states may be in conflict with the SNPCNA cycle attribute...

Page 216: ...Sampled DRCTM is synchronous to CLK and is only sampled with SWEND at the end of the snooping window At other times DRCTM is ignored and is not required to meet set up and hold times Relation to Othe...

Page 217: ...Pentium processor address pins by the 82496 Cache Controller This address should be used to perform a Pentium processor internal cache invalidation NV active or inquire cycle When Sampled EADS is driv...

Page 218: ...ignal Description EWBE inactive indicates that a write through cycle is posted in the 82496 Cache Controller 82491 Cache SRAM cache When Sampled EWBE goes inactive high in the CLK following ADS active...

Page 219: ...ERR Floating Point Error Floating point error reporting Output from Pentium processor pin H03 Synchronous to eLK Glitch Free Signal Description Refer to the Pentium Processor Data Book for a detailed...

Page 220: ...Pentium processor Flush due to the INVD or WBINVD instructions or Write Back due to the WBINVD instruction special cycle it must provide FLUSH to the 82496 Cache Controller The 82496 Cache Controller...

Page 221: ...processor will not pipeline any cycle into a Flush or Write Back special cycle CADS Once FLUSH has begun and FSIOUT is active all CADS and CRDY signals correspond to write backs caused by the flush op...

Page 222: ...t to Pentium processor pin M19 Asynchronous Signal Description When using the 82496 Cache Controller 82491 Cache SRAM second level cache the Pentium processor must be configured as a Master Device The...

Page 223: ...on Priorities Operation Initiating Signal Priority Initialization RESET Highest Flush FLUSH Sync SYNC lowest If a signal of Higher priority is asserted while a lower priority operation is in progress...

Page 224: ...s Pin Symbol Relation to Other Signals FLUSH Since RESET FLUSH and SYNC are all asynchronous FSIOUT is activated RESET when the 82496 Cache Controller is actually executing the operation For BIST SYNC...

Page 225: ...Z SLFTST Action Taken by 82496 Cache Controller 1 0 Self Test BIST 0 0 Outputs and 1 0 Floated High Z x 1 Normal Initialization Reset When Sampled HIGHZ is sampled as shown in the Initialization and C...

Page 226: ...PU Cache Line Indicates a hit to a line in the Pentium processor data or code caches Output from Pentium processor pin W02 Synchronous to ClK Signal Description Refer to the Pentium Processor Data Boo...

Page 227: ...Pentium processor data cache Output from Pentium processor pin M04 Input to 82496 Cache Controller pin E18 Input to 82491 Cache SRAM pin 62 Synchronous to ClK 82491 Cache SRAM internal Pull up Signal...

Page 228: ...cessor Hold Acknowledge Provides the Hold Acknowledge handshake from the CPU Output from Pentium processor pin 003 Synchronous to ClK Glitch Free Signal Description Refer to the Pentium Processor Data...

Page 229: ...HOLD Pentium processor Hold Provides the Hold handshake to the CPU Input to Pentium processor pin V05 Synchronous to ClK Signal Description Refer to the Pentium Processor Data Book for a detailed des...

Page 230: ...59 IBT IBT Instruction Branch Taken Indicates that a branch was taken Output from Pentium processor pin T19 Asynchronous Signal Description Refer to the Pentium Processor Data Book for a detailed desc...

Page 231: ...l Redundancy Errors Indicates an internal Parity or Functional Redundancy error occurred Output from Pentium processor pin CO2 Synchronous to ClK Glitch Free Signal Description Refer to the Pentium Pr...

Page 232: ...1 IGNNE IGNNE Ignore Numeric Error Ignore floating point error indication Input to Pentium processor pin 820 Asynchronous Signal Description Refer to the Pentium Processor Data Book for a detailed des...

Page 233: ...Initialization Forces the Pentium processor to begin execution at a known state Input to Pentium processor pin T20 Asynchronous Signal Description Refer to the Pentium Processor Data Book for a detail...

Page 234: ...TR INTR Maskable Interrupt Maskable interrupt request to the Pentium processor Input to Pentium processor pin N18 Asynchronous Signal Description Refer to the Pentium Processor Data Book for a detaile...

Page 235: ...d state if the inquire or back invalidation hits the first level cache INV is driven active to the CPU when SNPINV is sampled active by the 82496 Cache Controller and during replacements of modified l...

Page 236: ...In every lookup cycle the whole set will be read including the two parity bits The parity check will be done outside the TagRAM by regenerating the parity and comparing it to the read parity bits In c...

Page 237: ...line Instruction Indicates completion of an instruction in the U pipeline Output from Pentium processor pin J02 Synchronous to elK Signal Description Refer to the Pentium Processor Data Book for a det...

Page 238: ...ipeline Instruction Indicates completion of an instruction in the V pipeline Output from Pentium processor pin 801 Synchronous to elK Signal Description Refer to the Pentium Processor Data Book for a...

Page 239: ...KEN is valid with either NA or the first BRDY of the cycle whichever comes first Table 5 6 summarizes the cases when KEN is active and inactive Table 5 6 KEN Operation Cycle Type KEN Note locked cycl...

Page 240: ...with MRO sampled active BRDYC KEN is valid with either NA or the first BRDY of the cycle whichever comes first LOCK KEN is always driven inactive during locked cycles MKEN If MKEN is sampled inactive...

Page 241: ...e write of a processor read modify write sequence see Figure 5 26 Unlike the Intel486 DX CPU the Pentium processor automatically inserts at least one idle clock between two consecutive locked operatio...

Page 242: ...Signals Pin Symbol Relation to Other Signals CADS Address and cycle specification signals i e APIC CCACHE CD C CM IO CPCD CPWT CSCYC CW R CWAY KLOCK MAP MBT 3 0 MCACHE MCFA MSET MTAG NENE PALLC RDYSRC...

Page 243: ...MRO read only attributes have been determined Resolving KWEND quickly allows the non snoopable window between BGT and SWEND to be closed more quickly KWEND activation also allows the 82496 Cache Cont...

Page 244: ...um processor active CACHE must be issued after KWEND at which time KEN is valid CFG2 KWEND shares a pin with CFG2 CRDY Cycle progress implication rules specify that CRDY must be asserted for at least...

Page 245: ...s that the current bus cycle is locked Output from Pentium processor pin V03 Input to 82496 Cache Controller pin C17 Synchronous to ClK Glitch Free Signal Description Refer to the Pentium Processor Da...

Page 246: ...by the MBC Table 5 7 shows the line ratios selected by LR I 0 LR I 0 are driven by the 82496 Cache Controller to the 82491 Cache SRAM during RESET Table 5 7 82491 Cache SRAM Line Ratio Configuration...

Page 247: ...tes that the current cycle is either memory or 1 0 Output from Pentium processor pin A02 Input to 82496 Cache Controller pin G17 Synchronous to ClK Signal Description Refer to the Pentium Processor Da...

Page 248: ...be based on simulation results of these signals driving that load The 82496 Cache Controller configuration input MALDRV is used to select the buffer Refer to Table 7 14 for the buffer selection specif...

Page 249: ...new address issued by the 82496 Cache Controller will immediately appear at the memory bus When MALE is driven low the address at the input of the latch is latched Any subsequent address driven by the...

Page 250: ...rols the 82496 Cache Controller address output except for the sub line portion which has a separate output control MBAOE MAOE also provides the output enable for the memory line address parity MAP lat...

Page 251: ...control over the 82496 Cache Controller MAP line address output latch and the memory bus address parity MAP latch MBAOE MAOE and MBAOE together control the entire 82496 Cache Controller memory bus ad...

Page 252: ...AP is only sampled with SNPSTB activation When SNPSTB is not asserted MAP is a don t care signal and is not required to meet set up and hold times Relation to Other Signals Pin Symbol Relation to Othe...

Page 253: ...ring initialization and self test the 82496 Cache Controller does not perform address parity check when SNPSTB is issued In synchronous snoop mode MAPERR is driven to a valid level either active or in...

Page 254: ...2491 Cache SRAM that data supplied from memory should be written to the array one CLK after CRDY the linefill will be executed then During write cycles MAWEA indicates that the 82491 Cache SRAM should...

Page 255: ...ler sub line address will immediately appear at the memory bus When MBALE is driven low the sub line address at the latch input is latched Any subsequent sub line address driven by the 82496 Cache Con...

Page 256: ...ine address provided If MBAOE is sampled active the snoop write back begins at sub line address O This allows snoop write backs to begin at 0 or at the snooped sub line address and progress through th...

Page 257: ...r Signals MALE The 82496 Cache Controller memory bus address latch is completely controlled MBALE by MALE MBALE MAOE and MBAOE MAOE MAOE and MBAOE together control the entire 82496 Cache Controller me...

Page 258: ...PAR is driven to the corresponding CPU BE 7 0 level The MBE output is shared with the PAR pin and is operative following reset For a device configured in PARITY mode at reset time the MBE output funct...

Page 259: ...assertion In this case the 82491 Cache SRAM MBE outputs will be valid one CLK after the CADS of the memory bus cycle Refer to Figure 5 24 in the BLEC pin description If a cycle hits in the 82496 Cache...

Page 260: ...o be available If only one slice is required to be read or driven MSEL and MBRDY need not go active For read cycles the first piece of read data flows through to the CPU if no MZBT MBRDY assertion wit...

Page 261: ...the memory buffer in use to input or output data through the memory data bus pins MEOC MEOC switches the buffers to the next pending cycle and the last MBRDY must come before or on the ClK of MEOC ass...

Page 262: ...32 bits Driven low if the default operand size is 16 bits The Branch Trace Message Special Cycle is part of the Pentium processor execution tracing protocol If the execution tracing enable bit bit 1 i...

Page 263: ...3 0 MCACHE MCFA MSET MTAG NENE PALLC RDYSRC and SMLN are valid with CADS BT 3 0 The MBT 3 0 outputs of the cache controller reflect the BT 3 0 inputs during Branch Trace Message Special Cycles IBT Pen...

Page 264: ...write back cycles snoop write back cycles and cacheable read miss cycles i e read miss cycles in which PCD and LOCK are not asserted MCACHE is not asserted for I O special or locked cycles see Table 5...

Page 265: ...Signals Pin Symbol Relation to Other Signals CADS Address and cycle specification signals Le APIC CCACHE CD C CM IO CPCD CPWT CSCYC CW R CWAY KLOCK MAP MBT 3 0 MCACHE MCFA MSET MTAG NENE PALLC RDYSRC...

Page 266: ...ugh and MAOE and MBAOE are active outputs enabled the address is driven to the memory bus with CADS and SNPADS If a new cycle starts and MALE and MBALE are low and MAOE and MBAOE are also low the prev...

Page 267: ...STB is not asserted no snoop MSET MTAG MCFA need not meet any set up or hold time Relation to Other Signals Pin Symbol Relation to Other Signals CADS Address and cycle specification signals i e APIC C...

Page 268: ...Symbol Relation to Other Signals MBRDY In clocked memory bus mode the memory bus MSEL MFRZ MBRDY MDATA 7 0 MFRZ MZBT and MEOC pins are sampled synchronously with the rising edge of MOEC MSEL MCLK In...

Page 269: ...AM pin 42 Synchronous to ClK Signal Description MCYC is a one CLK pulse and when sampled by the 82491 Cache SRAM latches the current cycle address into one of the memory cycle address buffers It selec...

Page 270: ...en When the 82496 Cache Controller initiates a write cycle the write data is written to the appropriate memory buffer and CDTS is asserted If MDOE is active the first piece of write data is available...

Page 271: ...the memory buffers plus a full CPU ClK to read data into the CPU If properly done data on the memory bus can pe read in by asserting MBRDY and in the next full CPU ClK read into the CPU using BRDY MC...

Page 272: ...results of these signals driving that load The 82491 Cache SRAM configuration input MDLDRV is used to select the buffer Refer to Table 7 14 for the buffer selection specifications and the appropriate...

Page 273: ...ory output drivers When Sampled Since MDOE is a direct connection to the 82491 Cache SRAM memory output drivers MDOE must always be driven to a valid level When MDOE becomes active data in the 82491 C...

Page 274: ...if pipelining is used the next cycle flows through with a propagation delay MEOC is required for all memory bus cycles MEOC provides three functions in addition to switching memory bus cycles 1 It res...

Page 275: ...on the memory bus and the next cycle to flow through before CRDY is asserted MEOC is asserted before or on the same ClK as CRDY MEOC for cycle N 1 must be asserted at least one ClK after the CRDY of...

Page 276: ...must be returned active in order for the write cycle to be turned into an allocation i e MFRZ is ignored if either PALLC or MKEN are inactive MFRZ is sampled when MEOC goes active at the end of the w...

Page 277: ...enhance performance If an allocation is done following this dummy write cycle DRCTM must be asserted during the SWEND window of the line fill to put the allocated line in the M state MDLDRV MFRZ share...

Page 278: ...ve until the CLK of CRDY of the snoop write back If MHITM is asserted by any cache during snooping the bus master should back off from the bus to allow a snoop write back When Driven The snoop lookup...

Page 279: ...he memory bus into the 82491 Cache SRAM memory cycle buffer MISTB is used in strobed memory bus mode In clocked memory bus mode MISTB is the MBRDY input When Sampled MISTB is always sampled by the 824...

Page 280: ...second level cache If MCACHE is inactive the line is non cacheable regardless of MKEN PCD or LOCK activation cause MCACHE to be inactive MKEN is sampled during write through cycles that are potentiall...

Page 281: ...ained e g relative to MCLK As MOCLK is skewed relative to MCLK MDATA hold time and output valid delay skews with it The maximum MOCLK delay allowed is equal to the MCLK high time To be used effectivel...

Page 282: ...r Signals MCLK To be used effectively MOCLK must be the same frequency as MCLK but skewed from it This effectively increases data memory data bus hold time to main memory Main memory must sample the d...

Page 283: ...om the 82491 Cache SRAM memory cycle or write back buffers MOSTB is used only in strobed memory bus mode In clocked memory bus mode MOSTB is the MOCLK input When Sampled MOSTB is always sampled by the...

Page 284: ...2491 Cache SRAM requires an entire cache line from the memory bus Read Only cache lines are placed in the S state If MRO is returned active during KWEND DRCTM and MWB WT are ignored during SWEND The l...

Page 285: ...location In all other eLKs MRO need not follow set up and hold times Relation to Other Signals Pin Symbol Relation to Other Signals BRDY To make CPU accesses not cacheable MRO must be returned at leas...

Page 286: ...ers This would be necessary if the MBC began latching data from main memory prior to the snoop window closure and the snoop result was a hit to a modified line in another cache MSEL may stay inactive...

Page 287: ...he first transfer to initialize the burst counter Relation to Other Signals Pin Symbol Relation to Other Signals MSRDY MSEL qualifies the use of MSRDY Since MSEL acts as a qualifier for this signal it...

Page 288: ...ache SRAM operates in strobed mode If a CLK is detected on this pin any time after the falling edge of RESET the 82491 Cache SRAM enters clocked memory bus mode and the input becomes the memory CLK MC...

Page 289: ...THIT is valid one CLK after SNPCYC and remains valid until the next snoop cycle When Driven The snoop lookup is performed in the CLK in which SNPCYC is asserted The MTHIT snoop result is driven on the...

Page 290: ...on the ratio between the 82496 Cache Controller 82491 Cache SRAM s second level cache line size and its memory data bus width When Sampled MTR4 8 is sampled as shown in the Initialization and Configur...

Page 291: ...f memory may be designated as write through by making MWBJWT O for appropriate addresses DRCTM does not affect the 82496 Cache Controller if MWBJWT is sampled low or if MRO has been sampled active dur...

Page 292: ...pled LOW on the falling edge of RESET the 82491 Cache SRAM is configured to use all eight memory data bus pins MDATA 7 0 The necessary value of MX4 8 is based on the other configuration options chosen...

Page 293: ...an 0 the MBC must hold off any BRDY until that bursted item is read from the memory bus When Sampled In clocked mode MZBT is sampled in two places First MZBT is sampled on all MCLK rising edges in whi...

Page 294: ...transfer that occurs in region A The MZBT value sampled on clock n is used for the first transfer that occurs on any clock following clock n Figure 5 30 MZBT Sampling Relation to Other Signals Pin Sym...

Page 295: ...ocessor are known or not sampled For cycles which sample KWEND MKEN MRO the caching attributes are known one CLK after KWEND For cycles which do not sample KWEND the caching attributes may be known ea...

Page 296: ...T are ready on the CPU pins In all cases the 1 5 deep pipeline rule will be met Relation to Other Signals Pin Symbol Relation to Other Signals BLAST The ClK in which NA is issued to the CPU is depende...

Page 297: ...to the same page are not consecutive For example if a snoop write back cycle is issued between two normal memory bus cycles the NENE signal may go active but has no meaning since the snoop address int...

Page 298: ...09 NMI NMI Non maskable Interrupt Pentium processor non maskable interrupt Input to Pentium processor pin N19 Asynchronous Signal Description Refer to the Pentium Processor Data Book for a detailed de...

Page 299: ...ycle Potential allocate cycles are misses to the second level cache with PCD and PWT inactive PALLC is asserted upon the following sequence of Pentium processor signals 82496 Cache Controller Miss PCD...

Page 300: ...5 When Sampled PAR is a configuration option and must be driven either HIGH or LOW at reset If PAR is driven HIGH during RESET it becomes MBE after RESET goes inactive Relation to Other Signals Pin Sy...

Page 301: ...ity Disable Indicates CPU cycle cacheability Output from Pentium processor pin W04 Input to 82496 Cache Controller pin J16 Synchronous to ClK Signal Description Refer to the Pentium Processor Data Boo...

Page 302: ...K PCHK Parity Status Output Pentium processor parity status Output from Pentium processor pin R03 Synchronous to ClK Glitch Free Signal Description Refer to the Pentium Processor Data Book for a detai...

Page 303: ...Error Enable Determines if machine check interrupt is taken on a parity error Input to Pentium processor pin M18 Synchronous to elK Signal Description Refer to the Pentium Processor Data Book for a d...

Page 304: ...E INTERFACE 5 2 2 115 PRDY PRDY PRDY For use with Intel debug port Output from Pentium processor Signal Description Refer to the Pentium Processor Data Book for a detailed description of this signal I...

Page 305: ...gh Indicates CPU cycle write through attribute Output from Pentium processor pin S03 Input to 82496 Cache Controller pin 018 Synchronous to ClK Signal Description Refer to the Pentium Processor Data B...

Page 306: ...RFACE 5 2 2 117 RIS RIS RIS For use with Intel debug port Asynchronous Input Internal Pull up Resistor Signal Description Refer to the Pentium Processor Data Book for a detailed description of this si...

Page 307: ...91 Cache SRAM When low it indicates that the 82496 Cache Controller will provide the BRDY signals RDYSRC is active HIGH for CPU read cycles and I O cycles RDYSRC is inactive for Allocation replacement...

Page 308: ...tells the Pentium processor 82496 Cache Controller and 82491 Cache SRAM to sample all configuration inputs and begin in a known state See the specific configuration signals for set up and hold times r...

Page 309: ...2 it should operate in FLUSH Must be HIGH for proper Pentium processor 82496 Cache Controller operation BGT CLDRV Selects the driving strength of the 82496 Cache Controller 82491 Cache SRAM interface...

Page 310: ...Indicates the current locked cycle is misaligned Output from Pentium processor pin R04 Input to 82496 Cache Controller pin G16 Synchronous to ClK Signal Description Refer to the Pentium Processor Dat...

Page 311: ...nal Description When driven low to the 82491 Cache SRAM SEC2 indicates that each tag will represent two 82496 Cache Controller 82491 Cache SRAM cache lines in the 82491 Cache SRAM SRAM If SEC2 is driv...

Page 312: ...HZ pin description The self test results are obtained by latching CAHOLD in the first CLK that FSIOUT is inactive If CAHOLD is sampled HIGH self test completed successfully If CAHOLD is sampled LOW a...

Page 313: ...tem Power Management Interrupt Latches a power interrupt request Input to Pentium processor pin P18 Asynchronous Internal Pull up Signal Description Refer to the Pentium Processor Data Book for a deta...

Page 314: ...Power Management Interrupt Active Indicates that the CPU is operating in System Management Mode Output from Pentium processor pin T05 Asynchronous Signal Description Refer to the Pentium Processor Dat...

Page 315: ...hits to the same line may be snooped only once SMLN must be ignored by the MBC if the memory bus accesses to the same page are not consecutive For example if a snoop write back cycle is issued between...

Page 316: ...cle for which BGT is not yet issued The 82496 Cache Controller sometimes re issues these non committed cycles after the snoop write back has completed A snoop write back cycle is not pipelined into a...

Page 317: ...CNA is ignored during snoop write back cycles initiated with SNPADS CRDY Cycles initiated by SNPADS require CRDY but do not require other cycle progress signals BGT KWEND SWEND Snoop Address and SNPA...

Page 318: ...s in progress and during snoop write backs SNPBSY indicates to the MBC that the next snoop look up is delayed until two CLKs after SNPBSY goes inactive If SNPBSY is active one snoop request address is...

Page 319: ...and timing of 82496 Cache Controller snoop operations During clocked snooping operations SNPSTB SNPINV SNPNCA MBAOE MAOE and the address MCFA MSET MTAG and address parity MAP lines are sampled on the...

Page 320: ...in progress when SNPSTB is asserted between BGT and SWEND or during synchronization as in clocked and strobed snooping modes When Driven SNPCYC is always a valid 82496 Cache Controller output and is a...

Page 321: ...ted overriding other inputs or attributes e g SNPNCA As long as SNPINV is not asserted cache states are maintained according to the SNPNCA value When Sampled In synchronous snoop mode SNPINV is sample...

Page 322: ...e of RESET Clocked mode is selected by connecting the memory bus controller MBC snoop clock source to SNPMD thereby making SNPMD the snoop clock SNPCLK input When Sampled SNPMD is not used except when...

Page 323: ...troller need not put the line into S state If SNPNCA is inactive the 82496 Cache Controller tag state will change to S following the snoop operation To reduce bus traffic SNPNCA should be asserted whe...

Page 324: ...nly sampled with SNPSTB SNPSTB may be qualified by CLK SNPCLK or the falling edge of SNPSTB depending on the snoop mode and must meet set up and hold times to the edge being sampled When SNPSTB is not...

Page 325: ...ce SNPCYC is asserted and MHITM and MTHIT are driven to indicate the result of the snoop Snoops may be pipelined by latching a new snoop before the first has completed Pipelining is done by asserting...

Page 326: ...b line address o SNPCYC SNPSTB must not be reasserted for a new snoop until after SNPCYC is asserted for a previous snoop SNPINV SNPSTB latches SNPINV using MAOE as a qualifier SNPINV and SNPNCA provi...

Page 327: ...cache controller to change state as needed for the current cycle_ DRCTM and MWB WT influence the state change decision When Sampled SWEND need only be active for cycles requiring DRCTM and MWB WT to b...

Page 328: ...ted in the same ClK CFG1 SWEND shares a pin l Vith CFG1 DRCTM SWEND causes MWBfWT and DRCTM to be sampled KWEND BGT KWEND and SWEND may be asserted in the same ClK When KWEND and SWEND are applicable...

Page 329: ...ler completes all pending cycles and prevents further assertions of ADS while the synchronize operation is in progress The FSIOUT output signal indicates the start and end of the SYNC operation FSIOUT...

Page 330: ...is active all CADS and CRDY signals correspond with write backs caused by the synchronize operation FSIOUT The FSIOUT output signal indicates the start and end of the SYNC operation FSIOUT becomes act...

Page 331: ...mponent on the rising edge of TCK on TMS and TDI respectively Data is clocked out of the Pentium processor CPU Cache Chip Set on the falling edge of TCK on TDO In addition to using TCK as a free runni...

Page 332: ...testability chapter An internal pull up resistor is provided on TDI to ensure a known logic state if an open circuit occurs on the TDI path Note that when the value I is continuously shifted into the...

Page 333: ...MS signal as described in the testability chapter When not in the SHIFT IR or SHIFT DR state IDO is driven to a HIGH impedance state to allow connecting TDO of different devices in parallel When Drive...

Page 334: ...er To ensure detenninistic behavior of the TAP controller TMS is provided with an internal pull up resistor If boundary scan is not used TMS may be tied HIGH or left unconnected When Sampled TMS is sa...

Page 335: ...tinue unhindered During initialization the Pentium processor or 82496 Cache Controller initializes the instruction register such that the IDCODE instruction is loaded On power up the TAP controller is...

Page 336: ...rrent cycle is a write or a read cycle Output from Pentium processor pin N03 Input to 82496 Cache Controller pin C18 Input to 82491 Cache SRAM pin 58 Synchronous to ClK Signal Description Refer to the...

Page 337: ...If WAY is driven high the cycle will access way one If WAY is driven low the cycle will access way zero The 82491 Cache SRAM samples WAY with WRARR for normal write cycles and read hits which miss the...

Page 338: ...r to go into exclusive states if the 82496 Cache Controller itself is making a transition from E to M states or is already in M state e g from a previous cycle with DRCTM asserted This ensures that fo...

Page 339: ...high selects line 2 In configurations with 1 line per sector 1 2 4 5 WBA is driven low to the 82491 Cache SRAM during write back cycles In configurations with 2 lines per sector 3 WBA indicates which...

Page 340: ...Cache SRAM This signal is used by the 82491 Cache SRAM to detennine which buffer it will load the data to be written back into either the snoop write back buffer or the replacement write back buffer...

Page 341: ...rite back either a snoop write back from the snoop write back buffer or a replacement write back from the replacement write back buffer WBWE will be active for 2 CLKs if the write back is a replacemen...

Page 342: ...cide which way should be updated or what MRU value to write For read cycles which miss the MRU bit the 82491 Cache SRAM will update the MRU bit 1 CLK after WRARR is sampled active The WAY signal value...

Page 343: ...M or E state 3 A snoop hit to B causes a write back of the modified line from Write B before the line from Write A is written back Here the line modified by Write B is written to memory before the dat...

Page 344: ...Memory Bus Functional Description I 6...

Page 345: ......

Page 346: ...ycles This chapter begins with read cycles both cacheable and non cacheable It moves on to write cycles cacheable and non cacheable Snooping locked and I O cycles are also represented by examples in t...

Page 347: ...MRU bit also corresponding to the selected set The W R signal sampled low causes the 82491 Cache SRAM to drive its data pins onto the CPU data bus Since the 82496 Cache Controller detects an MRU hit i...

Page 348: ...g to the correct way The 82491 Cache SRAM drives the CPU data bus by the end of clock 9 Note that the wait state caused by the MRU miss is hidden due to the pipeline KEN is driven high to the CPU in t...

Page 349: ...sst Ss sst I I CRDY MCLK MSEl _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MDATA t 1I j aJD A J j I GD D 1D ID1 J4iI2 2 MBRDY SS5 SS S SS SS S i MEOC I I I I I I I I I I I I I STRO BEO MPOE MISTS l 1 1 f l l 1 I I 1...

Page 350: ...he current cycle from the 82496 Cache Controller When the memory bus has detennined the cacheability attribute of the cycle it drives the MKEN signal accordingly At this point the MBC drives the KWEND...

Page 351: ...NA or first BRDY Note that the CPU delays the new ADS due to AHOLD activation The CPU issues an ADS in clock 10 cycle B This read cycle also misses the cache directory Since the 82496 Cache Controlle...

Page 352: ...I MDOE I I I I I I I I I I I I I I I I I I I I I I I MDATA A1 A2 A3 A4 WB1 WB2 WB3 WB4 MISTB MOSTB 1 ts SIsx t L I 1 l 1 j I I 1 MEOC I I I I I I I I I i lJ I I I I I I I I I I I STROBED MODE MISTB 1...

Page 353: ...which is completed in clock 11 see BLAST BRDY In clock 13 the CPU starts flushing back the contents of the inquired line WBTYP will be valid during the write back ADS in order to inform the 82491 Cac...

Page 354: ...ransfer onto the memory bus Figure 6 4 Non Cacheable Read Miss Figure 6 4 illustrates a sequence of pipelined read misses that are non cacheable by the CPU The first two cycles A B are also non cachea...

Page 355: ...t t cp _ lil BRDYC IT I 1 1 II I IT BlEC Ir r I COB58 Figure 6 5 Write Hits to E or M State Cycles Figure 6 5 illustrates a sequence of Pentium processor memory write cycles that hit 82496 Cache Cont...

Page 356: ...he fourth BRDYC indicating the completion of the cycle Data is effectively written into the 82491 Cache SRAM ARRAY during the first half of clock 9 Since the Pentium processor will not pipeline a new...

Page 357: ...strobed mode MOSTB is used in place of MBRDY to indicate data transfer off of the memory bus Figure 6 6 Write Miss with No Allocation or Write Hit to S State Cycles Figure 6 6 illustrates a sequence...

Page 358: ...fer is collected in the 82491 Cache SRAM s CPU buffer in clock 5 The 82496 Cache Controller posts the transfer after MKEN is sampled inactive during KWEND in clock 6 If MKEN was sampled active during...

Page 359: ...I S I MSSSSSSSSSSSSSS OSSSS CACHE fl I I I I I I sssJ s SS S S S Sf D I IIII I BlEC AHDlDI I I I I I I I I I I 1 1 I I I I I I I I MClK MSEL MODEl I I I I I I I I I I I I I I I I I I I MDATA CI MBRDY...

Page 360: ...ith the memory bus write the Cache Controller serves a CPU read hit cycle B in clocks 4 to 9 note the wait state in clock 10 due to the write after read back to back cycles on the CPU bus In clock 8 t...

Page 361: ...indicates to the MBC that the memory bus should not be released between the Klocked cycles KLOCK will remain active from the beginning of the first cycle with CADS until CADS is issued for the last cy...

Page 362: ...mory bus after completion of the current cycle In clock 11 a similar locked sequence starts C D Since the last locked write was posted a new ADS is issued even before the CRDY of that write clock 12 T...

Page 363: ...I I In SNPINVtSNPNCA NOTE MCLK MSEL _ _ _ _ _ J J_ _ _ _J s fSS S S SS f y t 2sstS 2S S S S2SS tSS S t M t I J 1 I I I I I I I I I I I I I I MEDC STRtBED DDf I I I I I I I I I I I I I I I LH l MOSTB I...

Page 364: ...Cache Controller issues AHOLD clock 5 causing the CPU to float its address lines The 82496 Cache Controller issues WBWE WBTYP and WBA WBTYP and WBA would be active high indicating to the 82491 Cache...

Page 365: ...g the re issued in this example ADS in clock 19 After the Pentium processor write back has completed clock 17 the CPU issues in this example re issues the read miss cycle clock 19 In clock 21 the MBC...

Page 366: ...IuL AJ I I I I I CDTS CM IO CW R RDYSRC MCACHE BGT CNA CRDY MSEL I I i I i i i i I S 00S I f y M r i I I I I I I I I I I r k Ai J Bi 0 k C t s I I AI y I I I iii I i i 1 i MDOE 11 I I I I I I MDATA I...

Page 367: ...es BRDY clock 8 to both the 82496 Cache Controller and the CPU CRDY is activated in clock 9 indicating to the 82496 Cache Controller the completion of the cycle on the memory bus The 82496 Cache Contr...

Page 368: ...7 Electrical SpecificatiODS I...

Page 369: ......

Page 370: ...mount capacitors and interconnects are recommended for best high frequency electrical performance Inductance can be reduced by connecting capacitors directly to the Vcc and Vss planes with minimal tra...

Page 371: ...or electric fields Table 7 1 Absolute Maximum Ratings Case temperature under bias 65 C to 11 DoC Storage temperature 65 C to 150 C Voltage on any pin with respect to ground 0 5 Vee to Vee 0 5 V Supply...

Page 372: ...65 CS 60 MHz 3 9 III Input Leakage Current 15 uA Os VIN s Vee 8 ILO Output Leakage Current 15 uA Os VOUT s Vee 8 Tristate IlL Input Leakage Current 400 uA VIN 0 45V 5 IIH Input Leakage Current 200 uA...

Page 373: ...ly current is 2370 mA 11 9 W at 60 MHz 14 Not 100 tested Guaranteed by design characterization 15 VIL min and VIH max are not 100 tested Guaranteed by design characterization 7 6 A C SPECIFICATIONS Th...

Page 374: ...a loaded and an unloaded output buffer The most straight forward definition of flight time is the time difference between the loaded and unloaded output signals at the 50 Vcc voltage level as illustr...

Page 375: ...Time CDB10 Figure 7 1 Determination of Flight Time Figure 7 1 shows detennination of flight time based on the 50 Vcc level measurement of a 0 pF load output with reference to the 50 Vcc level of at t...

Page 376: ...e ledge is equivalent to the time required for an unloaded driver to reach the 50 Vcc level The oscillation if any seen at the ledge defines the measurement uncertainty for this technique To measure f...

Page 377: ...onfiguration signals HIGH during reset and the second to driving them LOW Tables 7 5 to 7 8 list the flight time and clock skew for the 66 MHz 256K byte CPU Cache Chip Set Tables 7 9 to 7 12 list the...

Page 378: ...Pentium Processor CC 82496 Cache Controller CS 82491 Cache SRAM Max Min Max CLKSkew Flight Time Flight Time Driver Receiver Driver Receiver n5 n5 n5 Buffer Type Buffer Type PP 00 063 CS COATAO 7 0 7...

Page 379: ...PP A6 A16 CC SETO 1O 0 2 2 S ZD6 ZD6a ZRS PP A3 A16 CS A2 A15 0 7 2 S ZD6 ZD6a ZR9 CC CFAO 1 PP A3 A4 0 2 9 5 ZD7 ZR6 CC CFA6 PPA5 0 2 9 5 ZD7 ZR6 CC SETO 10 PP A6 A16 0 2 9 5 ZD7 ZR6 CC CFAO 1 CS A2...

Page 380: ...C TAG4 11 PP A21 A28 0 2 3 2 Z07 ZR5 CCAP PPAP 0 2 2 7 Z07 ZR3 CC CFA2 4 PP A29 A31 0 2 3 2 Z07 ZR5 CC BTO BT3 PP BTO BT3 0 2 3 2 Z07 ZR5 PPAP CCAP 0 2 1 6 Z04 ZR8 PP SCYC CC SCYC 0 2 1 6 Z01 ZR7 PPPW...

Page 381: ...WEA 0 7 2 7 ZD9 ZD9a ZR9 CC BUS CS BUS 0 7 2 7 ZD9 ZD9a ZR9 CCWBA CSWBA 0 7 2 ZD9 ZD9a ZR9 CCWBWE CSWBWE 0 7 2 7 ZD9 ZD9a ZR9 CCWBTYP CS WBTYP 0 7 2 7 ZD9 ZD9a ZR9 CC BRDYC2 CS BRDYC 0 7 2 5 ZD9 ZD9a...

Page 382: ...a ZRS PP A6 A16 CC SETO 10 0 3 3 3 ZD6 ZD6a ZRS PP A3 A16 CS A2 A15 O S 3 3 ZD6 ZD6a ZR9 CC CFAO 1 PPA3 A4 0 3 10 ZD7 ZR6 CCCFA6 PPAS 0 3 10 ZD7 ZR6 CC SETO 10 PP A6 A16 0 3 10 ZD7 ZR6 CC CFAO 1 CSA2...

Page 383: ...7 CCAP PPAP 0 3 3 2 Z07 CCCFA2 4 PP A29 A31 0 3 3 7 Z07 CC BTO BT3 PP BTO BT3 0 3 3 7 Z07 PPAP CCAP 0 3 2 1 Z04 PPSCYC CCSCYC 0 3 2 1 Z01 PPPWT CCPWT 0 3 2 1 Z01 PPPCO CCPCO 0 3 2 1 Z01 PP M IO CC M I...

Page 384: ...CCWBTYP CS WBTYP 0 8 3 2 Z09 ZD9a ZR9 CC BROYC2 CS BROYC 0 8 3 0 Z09 ZD9a ZR9 CC BLEC CS BLEC 0 8 3 0 Z09 ZD9a ZR9 7 S 1 1 3 SO MHz 512 Kbyte Flight Times Table 7 13 to Table 7 16 list the flight time...

Page 385: ...A17 CC SETO 10 0 3 3 3 Z06 Z06a ZRB PP A3 A17 CS A1 A15 O B 3 3 Z06 Z06a ZR9 CC CFAO 1 PP A3 A4 0 3 10 6 Z07 ZR6 CC CFA5 6 PP A5 A6 0 3 10 6 Z07 ZR6 CC SETO 10 PPA7 A17 0 3 10 6 Z07 ZR6 CC CFAO 1 CS...

Page 386: ...C TAG4 11 PP A22 A29 0 3 3 7 lO7 lR5 CCAP PPAP 0 3 3 2 lO7 lR3 CC CFA2 3 PP A30 A31 0 3 3 7 lO7 lR5 CC BTO BT3 PP BTO BT3 0 3 3 7 lO7 lR5 PPAP CCAP 0 3 2 1 lO4 lRS PP SCYC CC SCYC 0 3 2 1 lO1 lR7 PP P...

Page 387: ...9 CCWRARR CSWRARR 0 8 3 0 Z09 l09a lR9 CCWAY CSWAY 0 8 3 2 lO9 l09a ZR9 CCMCYC CS MCYC 0 8 3 2 lO9 l0ga ZR9 CCMAWEA CSMAWEA 0 8 3 2 Z09 Z09a lR9 CC BUS CS BUS 0 8 3 2 lO9 l09a ZR9 CCWBA CSWBA 0 8 3 2...

Page 388: ...hoot for each signal within the signal group Maximum group average Time Beyond the Supply is the numeric average ofthe Maximum Time Beyond the Supply for each signal within the signal group Group aver...

Page 389: ...numeric average of the CPU CRAM 3 0ns Average Time time a signal may exceed Vcc or Vss CPU Cache 4 5ns Beyond Supply for all signals within a signal group CPU CCTL 3 0ns Signals whose overshoot is les...

Page 390: ...pS 18 19 20 21 250 t8 RESET INIT Setup Time 6 ns 7 9 To guarantee rec ognition on a given ClK edge 16 17 t9 RESET INIT Hold Time 1 5 ns 7 9 To guarantee rec ognition on a given ClKedge t10 RESET Pulse...

Page 391: ...ns 7 15 46 Asynchronous t29 TDI TMS Setup Time 5 ns 7 14 7 t30 TDI TMS Hold Time 13 ns 7 14 7 t31 TOO Valid Delay 3 20 ns 7 14 8 t32 TOO Float Delay 25 ns 7 14 8 46 t33 All Non Test Outputs Valid Del...

Page 392: ...lDA Valid Delay 1 5 8 ns 7 6 5 t51 BREQ Valid Delay 1 5 8 ns 7 6 t52 PCHK APCHK FERR IERR Valid 1 5 8 3 ns 7 6 5 Delay t53 IU IV IBT Valid Delay 1 5 10 ns 7 6 t54 BPO 3 PMO 1 Valid Delay 1 5 10 ns 7 6...

Page 393: ...ClKs 7 9 12 36 SlFTST SNPMD WWOR FlUSH Vcc Hold Time Referenced to Falling Edge of RESET t75 FlUSH SYNC Setup Time 6 ns 7 7 34 t76 FlUSH SYNC Hold Time 1 ns 7 7 34 t77 FlUSH SYNC Pulse Width Async 2 C...

Page 394: ...CRDY Hold Time 1 ns 7 7 t97 BGT CNA KWEND SWEND Setup 6 ns 7 7 Time t98 BGT CNA KWEND SWEND Hold 1 ns 7 7 Time t100 DRCTM MRO MWBIWT Setup Time 6 ns 7 7 24 t100a MKEN Setup Time 6 5 ns 7 7 24 t101 DR...

Page 395: ...E MBAOE SNPINV SNPNCA 6 ns 7 7 29 Selup Time 1131 MAOE MBAOE SNPINV SNPNCA 1 ns 7 7 29 Hold Time 1132 MAOE MBAOE SNPINV SNPNCA 6 ns 7 7 30 SelupTime 1133 MAOE MBAOE SNPINV SNPNCA 1 ns 7 7 30 Hold Time...

Page 396: ...alling Edge of RESET t155 BRDY CRDY Setup Time 5 ns 7 7 t156 BRDY CRDY Hold Time 1 ns 7 7 t160 MDATA Setup to ClK 5 ns 7 7 44 ClK before BRDY Active t161 MDATA Valid Delay From ClK 13 ns 7 6 49 ClK fr...

Page 397: ...7 Referenced to MCLK t184 MSRDY MSEL MEOC Hold Time 1 ns 7 7 Referenced to MCLK t185 MDATA Setup Time 5 ns 7 7 Referenced to MCLK t186 MDATA Hold Time 1 ns 7 7 Referenced to MCLK t187 MDATA Valid Dela...

Page 398: ...TB transition or 5 ns 7 11 MEOC Falling Edge t212 MDATA Hold From MISTB transition or 1 ns 7 11 MEOC Falling Edge t213 MDATA Valid Delay From Transition on 2 12 ns 7 13 MOSTB t214 MDATA Valid Delay Fr...

Page 399: ...ve any power spectrum peaking between 500 KHz and 1 3 of the ClK operating frequency 21 The amount of jitter present must be accounted for as a component of ClK skew between devices 22 Setup time is r...

Page 400: ...Vcc 2 level at gate of output device are guaranteed by design Not 100 tested 48 ClK Skew between 82491 cache SRAM and other devices Pentium processor 82496 cache controller and other C8Cs assumed to b...

Page 401: ...ns 7 9 To guarantee rec ognition on a given ClK edge 16 17 t9 RESET INIT Hold Time 1 5 ns 7 9 To guarantee rec ognition on a given ClK edge t10 RESET Pulse Width ClK and Vcc Stable 15 ClKs 7 9 11 17 t...

Page 402: ...ax Unit Fig Notes t30 TDI TMS Hold Time 13 ns 7 14 7 t31 TOO Valid Delay 3 20 ns 7 14 8 t32 TOO Float Delay 25 ns 7 14 8 46 t33 All Non Test Outputs Valid Delay 3 20 ns 7 14 8 10 t34 All Non Test Outp...

Page 403: ...Valid Delay 1 5 9 ns 7 6 5 t51 BREQ Valid Delay 1 5 9 ns 7 6 t52 PCHK APCHK FERR IERR Valid 1 5 9 3 ns 7 6 5 Delay t53 IU IV IBT Valid Delay 1 5 11 ns 7 6 t54 BPO 3 PMO 1 Valid Delay 1 5 11 ns 7 6 t55...

Page 404: ...ClKs 7 9 12 36 SlFTST SNPMD WWOR FlUSH Vcc Hold Time Referenced to Falling Edge of RESET t75 FLUSH SYNC Setup Time 6 5 ns 7 7 34 t76 FlUSH SYNC Hold Time 1 ns 7 7 34 t77 FlUSH SYNC Pulse Width Async...

Page 405: ...12 ns 7 10 28 46 MBTO 3 Float Delay t95 BRDY Setup Time 6 75 ns 7 7 t95a CRDY Setup Time 7 5 ns 7 7 t96 BRDY CRDY Hold Time 1 ns 7 7 t97 BGT CNA KWEND SWEND Setup 6 5 ns 7 7 Time t98 BGT CNA KWEND SWE...

Page 406: ...MBTO 3 Setup Time t125 MCFAO 6 MSETO 10 MTAGO 11 MAP 6 5 ns 7 8 31 MBTO 3 Hold Time t130 MAOE MBAOE SNPINV SNPNCA 6 5 ns 7 7 29 Setup Time t131 MAOE MBAOE SNPINV SNPNCA 1 ns 7 7 29 Hold Time t132 MAO...

Page 407: ...lling Edge of RESET t155 BRDY QRDY Setup Time 5 5 ns 7 7 t156 BRDY CRDY Hold Time 1 ns 7 7 t160 MDATA Setup to ClK ClK before 5 5 ns 7 7 44 BRDY Active t161 MDATA Valid Delay From ClK ClK from 13 ns 7...

Page 408: ...LK t182 MFRZ MZBT Hold Time 1 ns 7 7 Referenced to MCLK t183 MBRDY MSEL MEOC Setup Time 5 ns 7 7 Referenced to MCLK t184 MBRDY MSEL MEOC Hold Time 1 ns 7 7 Referenced to MCLK t185 MDATA Setup Time 5 n...

Page 409: ...old After Transition on MISTS or 10 ns 7 12 MOSTS t204 MSEL Setup Sefore Transition on 5 ns 7 12 MEOC t205 MSEL Hold After Transition on MEOC 1 ns 7 12 t206 MISTS MOSTS Transition to from 10 ns MEOC F...

Page 410: ...must be at least 10 microseconds 13 ClK skew between Pentium processor and 82496 cache controller assumed to be less than 0 2ns ClK skew is measured at 0 8V 1 5V and 2 0V of the rising edge of ClK 14...

Page 411: ...tive for first transfer on line fil s and all non cacheable transfers 45 MSEl sampled inactive resets burst counter Data is re driven beginning with data corresponding to first address requested 46 No...

Page 412: ...LK Signal CDB76 Tx 155 158 160 162 164 175 195 197 1100 1120 1122 1130 1132 1140 1155 1160 1181 1183 1185 Ty 156 159 161 163 165 175 196 198 1101 1121 1123 1131 1133 1141 1143 1156 1182 1184 1186 Tw 1...

Page 413: ...71 1151 Tv 19 Tw 142 172 1152 Tx 143 173 1153 Ty 110 113 Tz 18 Tw 192 1162 Tx 191 Ty Tz 193 1163 7 44 Ty t Tw Figure 7 9 Reset and Configuration Timings MAOE MBAOE MDOE MCFAx k J L MDATAx MALE MBAlE C...

Page 414: ...t213 t214 I ELECTRICAL SPECIFICATIONS STB Signal t 1 vJ 1 r COB80 Figure 7 11 Setup and Hold Timings to Strobes 1 5 V If J Signal 1 5 V If COB93 Figure 7 12 Setup and Hold Timings MxST STB 1 5 V Tx Si...

Page 415: ...r t35 Ts t36 Tu t32 Tv t29 Tw t30 Tx t31 Ty t33 Tz t34 Tx t28 7 46 TCK TOI r TMS ______ J Output r W I Signals oUI I Input T I Signals a l l l l Figure 7 14 Test Timings J Tx 1 5 V 1 CDB84 Figure 7 15...

Page 416: ...n _ I Tz y rTy COBBS Figure 7 16 Active Inactive Timings Each valid delay is specified for a 0 pF load The system designer should use I O buffer modeling to account for signal flight time delays Table...

Page 417: ...ClK SNPINV SNPNCA SNPSTB SWENO SYNC TCK TOI TMS TRST BGT CROY KWENO I N A ER6 ORCTM MRO MWB WT I N A ER7 ClK I N A ER8 MAP IN MAOE 1 OUT MAOE O 1 0 MCFA6 0 MSET10 0 MTAG11 0 MBT3 0 IN MAOE MBAOE 1 OUT...

Page 418: ...resent to ensure overshoot undershoot is within the acceptable range Maximum Overshoot Undershoot on Inputs 1 6 Volts without diodes Ringback is the absolute value of the maximum voltage at the receiv...

Page 419: ......

Page 420: ...8 1 0 Buffer Models I...

Page 421: ......

Page 422: ...ows the output buffer model Tables 8 1 and 8 2 shows the parameters used to specify these models Lp c CpT T COB65 Figure 8 1 First Order Input Buffer Table 8 1 Parameters Used in the Specification of...

Page 423: ...for each buffer type of the optimized interfaces These parameters supply the information to use in the circuits shown in Figures 8 1 and 8 2 to model the chip sets behavior in a given environment Tab...

Page 424: ...4 5 3 3 5 5 0 7 11 8 26 7 12 7 17 1 6 5 13 5 1 3 5 6 Failing PP 4 5 2 6 5 5 0 7 9 4 25 5 12 7 17 1 6 5 13 5 1 3 5 6 Z06a Rising PP 4 5 2 9 5 5 0 6 6 4 14 12 7 17 1 6 5 13 5 1 3 5 6 Falling PP 4 5 2 6...

Page 425: ...ation of Flight Time or Signal Quality Flight Time Signal Quality Driver dV dt min max Co max min Ro max min Cp max min Lp max min Receiver Cin max min Cp max min Lp max min Other Temp max min Vcc min...

Page 426: ...Parameters Legend PP Pentium Processor CC 82496 Cache Controller CS 82491 Cache SRAM Buffer Device Cp Lp Cin Type pF nH pF min max min max min max ER1 PP 0 8 10 2 5 2 20 6 1 1 1 5 ER2 PP 1 4 6 8 6 7...

Page 427: ...8 0 10 0 0 5 1 5 Falling CS 4 5 2 6 5 5 1 1 18 54 3 2 4 4 8 0 10 0 0 5 1 5 ED7 Rising CS 4 5 3 6 5 5 1 1 21 59 5 6 7 6 8 0 10 0 0 5 1 5 Falling CS 4 5 2 6 5 5 1 1 18 54 5 6 7 6 8 0 10 0 0 5 1 5 ED8 R...

Page 428: ...Diode Model The diode model should be added to the input model for both inputs and I O signals when desired Figure 8 4 shows the complete input model with the diodes added Vcc Rs T Cin 1 Rs _ Vss CDB8...

Page 429: ...and series resistance Table 8 9 provides the diode I V curve data for both Dl and D2 for each buffer type Table 8 8 Diode Parameter List Diode I V Input Model Type Buffer Type DriverMode Diode Curve T...

Page 430: ...792v 2 3ma 0 275v 4 91pa 0 275v 0 51 pa 0 826v 2 13ma 0 795v 2 7ma 0 3v 12 18pa 0 3v 1A9pa 0 83v 2 52ma 0 798v 3 13ma 0 325v 30 22pa 0 325v 4 4pa 0 834v 2 93ma 0 801v 3 57ma 0 35v 74 98pa 0 35v 12 96p...

Page 431: ...v 29 57ma 0 878v 15 97ma 0 835v 16 83ma 0 894v 29 14ma 0 848v 30 06ma 0 878v 16 46ma 0 835v 17 32ma 0 894v 29 63ma 0 848v 30 55ma 0 879v 16 94ma 0 836v 17 8ma 0 895v 30 12ma 0 848v 31 04ma 0 88v 17 43...

Page 432: ...ma 0 904v 42 43ma 0 856v 43 39ma 0 911 v 55 7Sma O S62v 56 76ma 0 904v 42 92ma 0 856v 43 88ma 0 912v 56 27ma 0 S62v 57 26ma 0 904v 43 42ma 0 857v 44 38ma 0 912v 56 77ma 0 S63v 57 75ma 0 905v 43 91ma 0...

Page 433: ...866v 67 68ma O 92v 75 61ma O 869v 76 62ma O 916v 67 18ma O 866v 68 18ma O 92v 76 11 ma O 869v 77 12ma O 917v 67 67ma O 867v 68 67ma O 92v 76 6ma O 869v 77 62ma O 917v 68 17ma O 867v 69 17ma O 92v 77...

Page 434: ...5v 0 31pa 0 805v 1 58ma 0 777v 2 11ma 0 275v 8 51 pa 0 275v 0 9pa 0 809v 1 98ma 0 781v 2 51ma 0 3v 21 11pa 0 3v 2 65pa 0 814v 2 37ma 0 784v 2 93ma 0 325v 52 38pa 0 325v 7 81pa 0 817v 2 77ma 0 786v 3 3...

Page 435: ...4 17ma O 875v 26 01ma O 832v 26 87ma O 859v 13 86ma O 818v 14 66ma O 876v 26 49ma O 832v 27 37ma O 86v 14 34ma O 819v 15 14ma O 876v 26 98ma O 833v 27 86ma O 86v 14 82ma O 82v 15 63ma O 877v 27 47ma O...

Page 436: ...39 69ma O 894v 51 63ma O 847v 52 56ma O 887v 39 28ma O 841v 40 19ma O 894v 52 12ma O 847v 53 06ma O 887v 39 77ma O 841v 40 68ma O 895v 52 61 rna O 848v 53 55ma O 887v 40 26ma O 842v 41 18ma O 895v 53...

Page 437: ...v 74 92ma O 856v 75 89ma O 9v 64 01ma O 852v 64 96ma O 904v 75 42ma O 856v 76 39ma O 9v 64 5ma O 852v 65 46ma O 905v 75 91ma O 856v 76 88ma O 9v 65ma O 852v 65 96ma O 905v 76 41ma O 856v 77 38ma O 901...

Page 438: ...824v 1 68ma 0 275v 2 19pa 0 275v 0 1pa 0 845v 1 77ma 0 828v 2 1ma 0 3v 5 44pa 0 3v 0 3pa 0 849v 2 18ma 0 831v 2 5ma 0 325v 13 49pa 0 325v 0 87pa 0 853v 2 57ma 0 834v 2 92ma 0 35v 33 48pa 0 35v 2 57pa...

Page 439: ...14 16ma 0 913v 26 25ma 0 883v 26 86ma 0 896v 14 1ma 0 869v 14 65ma 0 914v 26 74ma 0 883v 27 35ma 0 897v 14 58ma 0 87v 15 13ma 0 914v 27 23ma 0 883v 27 85ma 0 898v 15 06ma 0 87v 15 62ma 0 915v 27 72ma...

Page 440: ...1v 39 68ma 0 932v 51 88ma 0 898v 52 55ma 0 924v 39 53ma 0 892v 40 17ma 0 932v 52 37ma 0 898v 53 04ma 0 924v 40 02ma 0 892v 40 67ma 0 932v 52 87ma 0 898v 53 54ma 0 925v 40 51ma 0 892v 41 16ma 0 932v 53...

Page 441: ...ma 0 902v 64 45ma 0 941v 74 67ma 0 906v 75 3Sma 0 937v 64 26ma 0 90311 64 95ma 0 942v 75 17ma 0 906v 75 SSma 0 93Sv 64 75ma 0 903v 65 45ma 0 942v 75 67ma 0 906v 76 3Sma 0 93Sv 65 25ma 0 903v 65 94ma 0...

Page 442: ...Mechanical Specifications I 9...

Page 443: ......

Page 444: ...ge dimensions are 1 95 X 1 95 4 95cm X 4 95cm The 82491 Cache SRAM is packaged in a 84 pin plastic quad flat pack PQFP The package dimensions are 0 8 X 0 8 2 03cm X 2 03cm Table 9 1 CPU Cache Chip Set...

Page 445: ...llimeters Inches Min Max Notes Min Max Notes A 2 84 3 51 Solid Lid 0 112 0 138 Solid Lid A1 0 33 0 43 Solid Lid 0 013 0 017 Solid Lid A2 2 51 3 07 0 099 0 121 B 0 43 0 51 0 017 0 020 D 54 61 55 11 2 1...

Page 446: ...0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 000 o 0 o 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 447: ...Millimeters Inches Min Max Notes Min Max Notes A 2 84 3 51 Solid lid 0 112 0 138 Solid Lid A1 0 33 0 43 Solid Lid 0 013 0 017 Solid Lid A2 2 51 3 07 0 099 0 121 B 0 43 0 51 0 017 0 020 0 49 53 50 17...

Page 448: ...00000 000 0 0 0 0 a a 000 a 000 0 o 000 0 a 000 0 00000 000 o 0 o 0 o a o 0 000 0 0 000 o 0 o a a a 0 0 a o 0 0 0 0 0 0 o 0 000 a 0 o a 000 000 000 o a 0 000 a 0 a 000 a 0 a 0000000000 a 0 a 0 0 0 a a...

Page 449: ...ches Min Max Leadcount 84 Package Height 4 06 4 57 Standoff 0 51 1 02 Terminal Dimension 19 56 20 07 Package Body 16 43 16 59 Bumper Distance 20 24 20 39 Lead Dimension 12 70 REF Foot Radius Location...

Page 450: ...Thermal Specifications I 10...

Page 451: ......

Page 452: ...conductivity cements The laboratory testing was done by using Omega Bond part number OB 100 The thermocouple should be attached at a 90 angle as shown in the following figure When a heat sink is atta...

Page 453: ...Junction to Case and Case to Ambient Thermal Resistances for the 82496 Cache Controller With and Without a Heat Sink E JC E CA vs Airflow ftlmin 0 200 400 600 800 1000 With 0 35 Heat Sink 1 1 9 1 6 1...

Page 454: ...I THERMAL SPECIFICATIONS NOTE Additional heat sink and thermal information will be added as it becomes available Contact your local Intel Sales Office for the latest information 10 3...

Page 455: ......

Page 456: ...11 Testability I...

Page 457: ......

Page 458: ...e controller and 98 of the 82491 Cache Controller Memory devices 100 of the SRAM Array BIST will test the Pentium processor CPU micro code ROM cache controller TLB and 82496 Cache Controller 82491 cac...

Page 459: ...ent TAP controllers and test circuits in SHIFf DR state by shifting in test mode data through TMS pin b Shift out and examine the data of Pentium processor 82496 Cache Con1 roller or 82491 Cache SRAM...

Page 460: ...standard compatible 3 Test Data Registers There are at least four test data registers in each Pentium processor CPU Cache Chip Set component These are Bypass Register Device Identification Register RU...

Page 461: ...rapid movement of test data to and from other components on the board 11 2 2 2 BOUNDARY SCAN REGISTER The Boundary Scan Register is a shift register containing the boundary scan cells that are built w...

Page 462: ...code part number code and version code in the format shown in Figure 11 2 The content of the Device Identification Register changes with the stepping of the 82496 Cache Controller 82491 Cache SRAM or...

Page 463: ...de and the test data register to be accessed within each Pentium processor CPU Cache Chip Set component for one test task The instruction registers are four bits wide for the 82496 Cache Controller an...

Page 464: ...test data which is loaded into the boundary scan register output cells through component output pins It then allows the test data to propagate and to be captured on the corresponding boundary scan inp...

Page 465: ...r 82496 Cache Controller and 82491 Cache SRAM begins on the first rising edge of TCK after entering the Run Test ld1e state It requires at least S12K CLK CLK cycles at normal operating frequency in th...

Page 466: ...n of the device can continue unhindered During initialization the Pentium processor or 82496 Cache Controller initializes the instruction register such that the IDCODE instruction is loaded On power u...

Page 467: ...ate the fault in the Pentium processor CPU Cache Chip Set scan chain and control mechanism 11 2 5 Boundary Scan Register Cell The boundary scan register for each component contains a cell for each pin...

Page 468: ...2 043 044 045 046 047 OP6 048 049 050 051 052 053 054 055 OP7 056 057 058 059 060 061 062 063 IBT TOO Reserved includes the no connect NC signals on the Pentium processor The cells marked with are con...

Page 469: ...MTAG10 MTAG11 MCFA2 MCFA3 RESET MAOE MBAOE SNPCLK SNPSTB SNPINV FLUSH SYNC SNPNCA MBALE MALE jmaoe jooe jcfa4oe jcfa50e jcaoe Reservedoe jwbwtoe jnaoe TDO The following cells are control cells that ar...

Page 470: ...sts the control cells and their corresponding pins mdataoe01 mdataoe23 and mdataoe47 control the MDATA 7 0 pins cdataoeOl cdataoe23 and cdataoe47 control the CDATA 7 0 pins mbeoe controls the MBE PAR...

Page 471: ...ing the MRO signal 4 Write Os to every bit in the block of memory 5 Read the block the cache hits should be allIs 6 Repeat the process exchanging 0 for 1 and 1 for 0 In this example the code to test t...

Page 472: ...Supplemental Information I A...

Page 473: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 474: ...r are considered Intel confidential and proprietary and have not been documented in this publication This information is provided in the Supplement to the Pentium Processor User s Manual once the appr...

Page 475: ...nlel Corp tlntel Corp Tel 800 628 8686 FAX 317 875 8938 Four Commerce Park Square 2800 156th Avenue S E 23200 Chagnn Blvd SUite 600 SUite 105 MARYLAND Beachwood 44122 Bellevue 98007 tlntel Corp Tel 80...

Page 476: ...FAX 7081860 8532 Woodland Hills 91367 FLORIDA MTI Systems Tel 818 594 0404 1140 W Thorndale Avenue FAX 818 594 8233 Arrow Schweber Electronics Itasca 60143 Hamllton Avnet 400 Fairway Drive 102 Tel 708...

Page 477: ...15 1600 MTI Systems Sales 43 US RI 46 Pmebrook 07058 Tel 201 882 8780 FAX 201 882 8901 Self Certified Small Busmess per Federal AcquIsition Regulations Pioneer Standard 14A Madison Rd Fairfield 07004...

Page 478: ...5 3835 Beaverton 97005 1810 Greenville Avenue FAX 416 564 6036 Tel 503 643 7900 Richardson 75081 Pioneer Standard FAX 503 646 5466 Tel 214 235 9953 120 Bishop Way 163 Hamllton Avnet FAX 214 644 5064 B...

Page 479: ...thens Tel 30 1 3603741 FAX 30 1 3607501 IRELAND t M1Cro Marketing Taney Hall EgllOton Terrace Dundrum Dublin 14 Tel 353 1 298 9400 FAX 353 1 298 9828 ISRAEL t Eastronlcs limited Rozams 11 PO B 39300 T...

Page 480: ......

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