Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
611
DDR SDRAM Memory Controller—Intel
®
81341 and 81342
7.3.4.3
DDR ECC Checking
When enabled, the ECC logic uses the following ECC read algorithm. This algorithm
corrects the data before it's driven onto the internal bus. The ECC algorithm for a read
transaction is:
Read 64-bit data and 8-bit ECC
Compute the syndrome by passing the 64-bit data through the G-Matrix and XORing the
8-bit result with the 8-bit ECC
if the syndrome <> 0 {ECC Error}
Look up in H-matrix to determine error type
Register the address where the error occurred
if error is correctable {single bit}
if single-bit error correction is enabled
Correct data
Send corrected data to internal bus
if single bit error reporting is enabled
Interrupt core for software scrubbing
else {uncorrectable}
if the read cycle is
not
part of a RMW cycle {read}
Target-Abort the Internal Bus read transaction.
else {write requiring RMW}
Merge the new data portion with the read data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
if multi-bit error reporting is enabled
Interrupt the core for uncorrectable error
When the DMCU reads the ECC code from the memory subsystem, it is compared
(XORed) with an ECC that the DMCU generates from the data read from the memory.
The result is called the syndrome.
shows how the DMCU decodes the
syndrome for DDR SDRAM read cycles.
Table 370. Syndrome Decoding
Error Type
Symptom
None
The syndrome is 0000 0000.
Single-Bit
Use the H-Matrix in
to determine which bit the DMCU inverts to fix the error.
Multi-Bit
When the Syndrome does not match an 8-bit value in the H-matrix, the error is uncorrectable
