Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
1029
Peripheral Registers—Intel
®
81341 and 81342
21.6.1.3 SRAM Memory Controller
The SRAM Memory Controller is allocated 128 Bytes of PMMR registers space and is
always located at 1500H relative to the PMMRBAR.
Use the following equation to calculate the actual register address:
Internal Bus Address = P SMCU Base Address Register Offset.
Table 643. SMCU Base Address Offset.
Unit
SMCU Base Address Offset
(Relative to PMMRBAR)
SRAMMCU
+1500H
Table 644. SRAM Memory Controller
Register Description (Name)
Registe
r Size in
Bits
Internal Bus Address Offset
(Relative to SMCU Base
Address Offset)
SRAM Base Address Register — SRAMBAR
32
+00H
SRAM Upper Base Address Register — SRAMUBAR
32
+04H
SRAM ECC Control Register — SECR
32
+08H
SRAM ECC Log Register — SELOGR
32
+0CH
SRAM ECC Address Register — SEAR
32
+10H
SRAM ECC Context Register — SECAR
32
+14H
SRAM ECC Test Register — SECTST
32
+18H
SRAM Parity Control and Status Register — SPARCSR
32
+1CH
SRAM Parity Address Register — SPAR
32
+20H
SRAM Parity Upper Address Register — SPUAR
32
+24H
SRAM Parity Context Address Register — SPCAR
32
+28H
SRAM Memory Controller Interrupt Status Register — SMCISR
32
+2CH
Reserved
32
+30H
Reserved
32
+34
Reserved
x
+38H t7FH
