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Intel 80C186EC, Manual

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Intel 80C186EC Manual Download Page 36

80C186EC/188EC, 80L186EC/188EC

Relative Timings (80C186EC-25/20/13, 80L186EC-16/13)

NOTES:

1. Assumes equal loading on both pins.
2. Can be extended using wait states.
3. Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the
8259A module going active. This is not directly measureable by the user. For interrupt pin INT7 the delay from an active
signal to an active input to the CPU would actually be twice the T

IRES

value since the signal must pass through two 8259A

modules.
4. See INTA Cycle Waveforms for definition.
5. To guarantee interrupt is not spurious.

Serial Port Mode 0 Timings (80C186EC-25/20/13, 80L186EC-16/13)

Symbol

Parameter

Min

Max

Unit

Notes

RELATIVE TIMINGS

T

XLXL

TXD Clock Period

T (n

a

1)

ns

1, 2

T

XLXH

TXD Clock Low to Clock High (N

l

1)

2T

b

35

2T

a

35

ns

1

T

XLXH

TXD Clock Low to Clock High (N

e

1)

T

b

35

T

a

35

ns

1

T

XHXL

TXD Clock High to Clock Low (N

l

1)

(n

b

1) T

b

35

(n

b

1) T

a

35

ns

1, 2

T

XHXL

TXD Clock High to Clock Low (N

e

1)

T

b

35

T

a

35

ns

1

T

QVXH

RXD Output Data Setup to TXD

(n

b

1)T

b

35

ns

1, 2

Clock High (N

l

1)

T

QVXH

RXD Output Data Setup to TXD

T

b

35

ns

1

Clock High (N

e

1)

T

XHQX

RXD Output Data Hold after TXD

2T

b

35

ns

1

Clock High (N

l

1)

T

XHQX

RXD Output Data Hold after TXD

T

b

35

ns

1

Clock High (N

e

1)

T

XHQZ

RXD Output Data Float after Last

T

a

20

ns

1

TXD Clock High

T

DVXH

RXD Input Data Setup to TXD

T

a

20

ns

1

Clock High

T

XHDX

RXD Input Data Setup after TXD

0

ns

1

Clock High

NOTES:

1. See Figure 13 for Waveforms.
2. n is the value in the BxCMP register ignoring the ICLK bit.

36

Summary of Contents for 80C186EC

Page 1: ...Selects with Integral Wait State Generator Ð Memory Refresh Control Unit Ð Power Management Unit Ð On Chip Oscillator Ð System Level Testing Support ONCE Mode Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Y Low Power Operating Modes Ð Idle Mode Freezes CPU Clocks but Keeps Peripherals Active Ð Powerdown Mode Freezes All Internal Clocks Ð Powersave Mode Divides All Clocks by Pro...

Page 2: ...ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 Package Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀ 24 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 25 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 CONTENTS PAGE Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 29 PDTMR Pin Dela...

Page 3: ...80C186EC 188EC 80L186EC 188EC 272434 1 NOTE Pin names in parentheses apply to the 80C188EC 80L188EC Figure 1 80C186EC 80L186EC Block Diagram 3 ...

Page 4: ...tions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instructions and fully static oper ation The bus interface unit BIU is the same as that found on the original 186 family products ex cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is u...

Page 5: ...Two cascaded 8259A compatible Programma ble Interrupt Controllers Ð 3 Channel Timer Counter Unit Ð 2 Channel Serial Communications Unit Ð 4 Channel DMA Unit Ð 10 Output Chip Select Unit Ð 32 bit Watchdog Timer Unit Ð I O Port Unit Ð Refresh Control Unit Ð Power Management Unit The registers associated with each integrated pe ripheral are contained within a 128 x 16 bit register file called the Per...

Page 6: ...H SCU 1 Count 74H SCU 1 Control 76H SCU 1 Status 78H SCU 1 RBUF 7AH SCU 1 TBUF 7CH Reserved 7EH Reserved PCB Function Offset 80H GCS0 Start 82H GCS0 Stop 84H GCS1 Start 86H GCS1 Stop 88H GCS2 Start 8AH GCS2 Stop 8CH GCS3 Start 8EH GCS3 Stop 90H GCS4 Start 92H GCS4 Stop 94H GCS5 Start 96H GCS5 Stop 98H GCS6 Start 9AH GCS6 Stop 9CH GCS7 Start 9EH GCS7 Stop A0H LCS Start A2H LCS Stop A4H UCS Start A6...

Page 7: ...A Unit is comprised of two modules with two channels each All four channels are identical in operation DMA transfers can take place from memory to mem ory I O to memory memory to I O or I O to I O DMA requests can be external on the DRQ pins internal from Timer 2 or a serial channel or soft ware initiated The DMA Unit transfers data as bytes only Each data transfer requires at least two bus cycles...

Page 8: ...acteristics for the 80C186EC in the Plastic Quad Flat Pack JEDEC PQFP the EIAJ Quad Flat Pack QFP and the Shrink Quad Flat Pack SQFP For complete package specifications and information see the Intel Packaging Outlines and Dimensions Guide Order Number 231369 Prefix Identification Table 1 lists the prefix identifications Table 1 Prefix Identification Prefix Note Package Temperature Type Range QFP E...

Page 9: ... state or type with a i e H X H Q In this example when the pin is configured as P3 0 then its hold output state is H X when configured as RXI1 its output state is H Q All pins float while the processor is in the ONCE Mode with the exception of OSCOUT Table 1 Pin Description Nomenclature Symbol Description P Power Pin apply a VCC voltage G Ground connect to VSS I Input only pin O Output only pin I ...

Page 10: ...ing edge low to high transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location 0FFFF0H RESOUT O Ð H 0 RESet OUTput that indicates the processor is currently in the reset state RESOUT will remain active as long as R 1 RESIN remains active I 0 P 0 PDTMR I O A L H WH Power Down TiMeR pin normally connected to an external capacitor that determines the am...

Page 11: ...TA bus During the address phase of the bus cycle address bits 0 AD7 0 R Z through 12 0 through 7 on the 80C188EC are presented on I 0 the bus and can be latched using ALE Data information is P 0 transferred during the data phase of the bus cycle S2 0 O Ð H Z Bus cycle Status are encoded on these pins to provide bus transaction information S2 0 are encoded as follows R 1 I 1 P 1 S2 S1 S0 Bus Cycle ...

Page 12: ...service other bus R Z requests such as HOLD while LOCK is active This pin is I X configured as a weakly held high input while RESIN is active P X and must not be driven low HOLD I A L Ð HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instruction boundaries that are not LOCKed HLDA O Ð H ...

Page 13: ...hin the address limitations P1 3 GCS3 P X P 1 programmed by the user When not programmed as a P1 4 GCS4 Chip Select each pin may be used as a general purpose P1 5 GCS5 output port P1 6 GCS6 P1 7 GCS7 T0OUT O Ð H Q Timer OUTput pins can be programmed to provide single clock or continuous waveform generation depending on T1OUT R 1 the timer mode selected I Q P X T0IN I A L Ð Timer INput is used eith...

Page 14: ... I X P X P2 6 BCLK1 I O A L H X Baud CLocK input can be used as an alternate clock source for each of the integrated serial channels The P2 2 BCLK0 A E R Z BCLK inputs are multiplexed with I O Port functions The I X BCLK input frequency cannot exceed 2 the operating P X frequency of the processor P2 5 TXD1 I O A L H Q Transmit Data output provides serial data information The TXD outputs are multip...

Page 15: ...8 60 AD9 A9 59 AD10 A10 58 AD11 A11 57 AD12 A12 56 AD13 CAS0 55 A13 CAS0 AD14 CAS1 54 A14 CAS1 AD15 CAS2 53 A15 CAS2 A16 S3 77 A17 S4 76 A18 S5 75 A19 S6 ONCE 74 Bus Control Name Pin ALE 52 BHE RFSH 51 S0 78 S1 79 S2 80 RD 50 WR 49 READY 85 DEN 47 DT R 46 LOCK 48 HOLD 44 HLDA 45 INTA 34 Power and Ground Name Pin VCC 13 VCC 14 VCC 38 VCC 62 VCC 67 VCC 69 VCC 86 VSS 12 VSS 15 VSS 37 VSS 39 VSS 61 VS...

Page 16: ...NTA 35 NCS N C 36 WDTOUT 37 VSS 38 VCC 39 VSS 40 INT4 41 INT5 42 INT6 43 INT7 44 HOLD 45 HLDA 46 DT R 47 DEN 48 LOCK 49 WR 50 RD Pin Name 51 BHE RFSH 52 ALE 53 AD15 A15 54 AD14 A14 55 AD13 A13 56 AD12 A12 57 AD11 A11 58 AD10 A10 59 AD9 A9 60 AD8 A8 61 VSS 62 VCC 63 AD7 64 AD6 65 AD5 66 AD4 67 VCC 68 VSS 69 VCC 70 AD3 71 AD2 72 AD1 73 AD0 74 A19 S6 ONCE 75 A18 S5 Pin Name 76 A17 S4 77 A16 S3 78 S0 ...

Page 17: ...80C186EC 188EC 80L186EC 188EC 272434 3 NOTE This is the FPO number location indicated by X s Figure 4 100 Pin Plastic Quad Flat Pack Package PQFP 17 x ...

Page 18: ...C 17 VCC 41 VCC 65 VCC 70 VCC 72 VCC 89 VSS 15 VSS 18 VSS 40 VSS 42 VSS 64 VSS 71 VSS 90 Processor Control Name Pin RESIN 11 RESOUT 10 CLKIN 13 OSCOUT 14 CLKOUT 9 TEST BUSY 86 TEST PEREQ VSS 84 NCS N C 38 ERROR VCC 87 PDTMR 12 NMI 85 INT0 33 INT1 34 INT2 35 INT3 36 INT4 43 INT5 44 INT6 45 INT7 46 I O Name Pin UCS 91 LCS 92 P1 7 GCS7 93 P1 6 GCS6 94 P1 5 GCS5 95 P1 4 GCS4 96 P1 3 GCS3 97 P1 2 GCS2 ...

Page 19: ...INT1 35 INT2 36 INT3 37 INTA 38 NCS N C 39 WDTOUT 40 VSS 41 VCC 42 VSS 43 INT4 44 INT5 45 INT6 46 INT7 47 HOLD 48 HLDA 49 DT R 50 DEN Pin Name 51 LOCK 52 WR 53 RD 54 BHE RFSH 55 ALE 56 AD15 A15 57 AD14 A14 58 AD13 A13 59 AD12 A12 60 AD11 A11 61 AD10 A10 62 AD9 A9 63 AD8 A8 64 VSS 65 VCC 66 AD7 67 AD6 68 AD5 69 AD4 70 VCC 71 VSS 72 VCC 73 AD3 74 AD2 75 AD1 Pin Name 76 AD0 77 A19 S6 ONCE 78 A18 S5 7...

Page 20: ...80C186EC 188EC 80L186EC 188EC 272434 4 NOTE This is the FPO number location indicated by X s Figure 5 Quad Flat Pack EIAJ Pinout Diagram 20 x ...

Page 21: ...T 6 TEST BUSY 83 NMI 82 INT0 30 INT1 31 INT2 32 INT3 33 INT4 40 INT5 41 INT6 42 INT7 43 INTA 34 PEREQ VSS 81 ERROR VCC 84 NCS N C 35 PDTMR 9 Power and Ground VCC 13 VCC 14 VCC 38 VCC 62 VCC 67 VCC 69 VCC 86 VSS 12 VSS 15 VSS 37 VSS 39 VSS 61 VSS 68 VSS 87 I O UCS 88 LCS 89 P1 0 GCS0 97 P1 1 GCS1 96 P1 2 GCS2 95 P1 3 GCS3 94 P1 4 GCS4 93 P1 5 GCS5 92 P1 6 GCS6 91 P1 7 GCS7 90 P2 0 RXD0 16 P2 1 TXD0...

Page 22: ...A 35 NSC N C 36 WDTOUT 37 VSS 38 VCC 39 VSS 40 INT4 41 INT5 42 INT6 43 INT7 44 HOLD 45 HLDA 46 DT R 47 DEN 48 LOCK 49 WR 50 RD Pin Name 51 BHE RFSH 52 ALE 53 AD15 A15 54 AD14 A14 55 AD13 A13 56 AD12 A12 57 AD11 A11 58 AD10 A10 59 AD9 A9 60 AD8 A8 61 VSS 62 VCC 63 AD7 A7 64 AD6 A6 65 AD5 66 AD4 67 VCC 68 VSS 69 VCC 70 AD3 71 AD2 72 AD1 73 AD0 74 A19 ONCE 75 AD18 Pin Name 76 A17 77 A16 78 S0 79 S1 8...

Page 23: ...80C186EC 188EC 80L186EC 188EC 272434 5 NOTE This is the FPO number location indicated by X s Figure 6 100 Pin Shrink Quad Flat Pack Package SQFP 23 x ...

Page 24: ...e TA the ambient temperature can be calculated from iCA thermal resistance from the case to ambi ent with the following equation TA e TC b P iCA Typical values for iCA at various airflows are given in Table 9 P the maximum power consumptionÐ specified in Watts is calculated by using the maxi mum ICC and VCC of 5 5V Table 9 Thermal Resistance iCA at Various Airflows in C Watt Airflow in ft min m se...

Page 25: ...nditions may affect device reliability Recommended Connections Power and ground connections must be made to multiple VCC and VSS pins Every 80C186EC based circuit board should include separate power VCC and ground VSS planes Every VCC pin must be connected to the power plane and every VSS pin must be connected to the ground plane Liberal de coupling capacitance should be placed near the processor ...

Page 26: ...s 5 7 80C186EC20 100 mA Note 5 80C186EC13 100 mA Note 5 CIN Input Pin Capacitance 0 15 pF TF e 1 MHz COUT Output Pin Capacitance 0 15 pF TF e 1 MHz Note 6 NOTES 1 These pins have an internal pull up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified on any of these pins may invoke a factory test mode 2 Tested by outputs being floated by invoki...

Page 27: ...6EC 13 30 mA CIN Input Pin Capacitance 0 15 pF TF e 1 MHz COUT Output Pin Capacitance 0 15 pF TF e 1 MHz Note 6 NOTES 1 These pins have an internal pull up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified on any of these pins may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 3 Measure...

Page 28: ...Mode Note 5 80L186EC 16 50 mA CIN Input Pin Capacitance 0 15 pF TF e 1 MHz COUT Output Pin Capacitance 0 15 pF TF e 1 MHz Note 6 NOTES 1 These pins have an internal pull up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified on any of these pins may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserti...

Page 29: ... allow the crystal or resonator circuit to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted i e a device reset while in Pow erdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabilized To calculate the value of capacitor to use to provide a desired delay use the equation 440 c t e CPD 5V 25 C Where t e desired delay in seconds ...

Page 30: ... 17 ns 1 4 T CLKOUT Period 2 TC ns 1 TPH CLKOUT High Time T 2 b 5 T 2 a 5 ns 1 TPL CLKOUT Low Time T 2 b 5 T 2 a 5 ns 1 TPR CLKOUT Rise Time 1 6 ns 1 5 TPF CLKOUT Fall Time 1 6 ns 1 5 OUTPUT DELAYS TCHOV1 ALE S2 0 DEN DT R 3 17 ns 1 4 6 7 BHE RFSH LOCK A19 16 TCHOV2 GCS0 7 LCS UCS NCS RD WR 3 20 ns 1 4 6 8 TCLOV1 BHE RFSH DEN LOCK RESOUT 3 17 ns 1 4 6 HLDA T0OUT T1OUT A19 16 TCLOV2 RD WR GCS7 0 LC...

Page 31: ...ES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies...

Page 32: ...ns 1 4 6 AD7 0 A15 8 NCS INTA S2 0 A19 16 TCHOF RD WR BHE RFSH DT R LOCK 0 25 0 30 ns 1 S2 0 A19 16 TCLOF DEN AD15 0 AD7 0 A15 8 0 25 0 30 ns 1 INPUT REQUIREMENTS TCHIS TEST NMI T1IN T0IN READY 10 10 ns 1 9 CTS1 0 BCLK1 0 P3 4 P3 5 TCHIH TEST NMI T1IN T0IN READY 3 3 ns 1 9 CTS1 0 BCLK1 0 P3 4 P3 5 TCLIS AD15 0 AD7 0 READY 10 10 ns 1 10 TCLIH AD15 0 AD7 0 READY 3 3 ns 1 10 TCLIS HOLD RESIN PEREQ ER...

Page 33: ...3 28 ns 1 4 6 TCLOV2 RD WR AD15 0 AD7 0 A15 8 BHE 3 32 ns 1 4 6 RFSH NCS INTA DEN TCLOV3 GSC7 0 LCS UCS 3 34 ns 1 4 6 TCLOV4 S2 0 A19 16 3 37 ns 1 4 6 TCHOF RD WR BHE RFSH DT R LOCK 0 30 ns 1 S2 0 A19 16 TCLOF DEN AD15 0 AD7 0 A15 8 0 35 ns 1 INPUT REQUIREMENTS TCHIS TEST NMI T1IN T0IN READY 20 ns 1 9 CTS1 0 BCLK1 0 P3 4 P3 5 TCHIH TEST NMI T1IN T0IN READY 3 ns 1 9 CTS1 0 BCLK1 0 P3 4 P3 5 TCLIS A...

Page 34: ...UT Period 2 TC ns 1 TPH CLKOUT High Time T 2 b 5 T 2 a 5 ns 1 TPL CLKOUT Low Time T 2 b 5 T 2 a 5 ns 1 TPR CLKOUT Rise Time 1 9 ns 1 5 TPF CLKOUT Fall Time 1 9 ns 1 5 OUTPUT DELAYS TCHOV1 S2 0 DT R BHE LOCK 3 25 ns 1 4 6 7 TCHOV2 LCS UCS DEN A19 16 RD WR NCS 3 30 ns 1 4 6 8 WDTOUT ALE TCHOV3 GCS7 0 3 32 ns 1 4 6 TCLOV1 LOCK RESOUT HLDA T0OUT T1OUT 3 25 ns 1 4 6 TCLOV2 RD WR AD15 0 AD7 0 A15 8 BHE ...

Page 35: ... Falls 2T b 10 ns TPLLL Chip Select Valid before ALE Falls 2T b 10 ns 1 TLLAX AD Hold after ALE Falls 2T b 10 ns TLLWL ALE Falling to WR Falling 2T b 15 ns 1 TLLRL ALE Falling to RD Falling 2T b 15 ns 1 TWHLH WR Rising to Next ALE Rising 2T b 10 ns 1 TAFRL AD Float to RD Falling 0 ns TRLRH RD Active Pulse Width 2T b 5 ns 2 TWLWH WR Active Pulse Width 2T b 5 ns 2 TRHAX RD Rising to Next Address Act...

Page 36: ... Parameter Min Max Unit Notes RELATIVE TIMINGS TXLXL TXD Clock Period T n a 1 ns 1 2 TXLXH TXD Clock Low to Clock High N l 1 2T b 35 2T a 35 ns 1 TXLXH TXD Clock Low to Clock High N e 1 T b 35 T a 35 ns 1 TXHXL TXD Clock High to Clock Low N l 1 n b 1 T b 35 n b 1 T a 35 ns 1 2 TXHXL TXD Clock High to Clock Low N e 1 T b 35 T a 35 ns 1 TQVXH RXD Output Data Setup to TXD n b 1 T b 35 ns 1 2 Clock Hi...

Page 37: ...ion to see how timings vary with load capacitance Specifications are measured at the VCC 2 crossing point unless otherwise specified See AC Timing Waveforms for AC specification definitions test pins and illustrations 272434 6 CL e 50 pF for all signals Figure 7 AC Test Load AC TIMING WAVEFORMS 272434 7 Figure 8 Input and Output Clock Waveforms 37 ...

Page 38: ...80C186EC 188EC 80L186EC 188EC 272434 8 Figure 9 Output Delay and Float Waveforms 272434 9 Figure 10 Input Setup and Hold 272434 10 Figure 11 Relative Interrupt Signal Timings 38 ...

Page 39: ...80C186EC 188EC 80L186EC 188EC 272434 11 Figure 12 Relative Signal Waveform 272434 12 Figure 13 Serial Port Mode 0 Waveform 39 ...

Page 40: ...ystal to the device RESIN must remain active until both VCC and CLKOUT are stable the length of time is application specific and de pends on the startup characteristics of the crystal circuit The RESIN pin is designed to operate cor rectly using a RC reset circuit but the designer must ensure that the ramp time for VCC is not so long that RESIN is never sampled at a logic low level when VCC reache...

Page 41: ...zation occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high solid line then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low dashed line then CLKOUT will not be affected Pin names in parentheses apply to 80C188EC 80L188EC 41 ...

Page 42: ...zation occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high solid line then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low dashed line then CLKOUT will not be affected Pin names in parentheses apply to 80C188EC 80L188EC 42 ...

Page 43: ... figure is the relationship of the various bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application 272434 17 Pin names in parentheses apply to 80C188EC 80L188EC Figure 18 Memory Read I O Read Instruction Fetch and Refresh Waveforms 43 ...

Page 44: ...80C186EC 188EC 80L186EC 188EC 272434 18 Pin names in parentheses apply to 80C188EC 80L188EC Figure 19 Memory Write and I O Write Cycle Waveforms 44 ...

Page 45: ...AD15 0 AD7 0 lines will float during T1 Otherwise the AD15 0 AD7 0 lines will continue to drive during T1 data is invalid All other control lines are in their inactive state 2 All address lines drive zeros while in Powerdown or Idle Mode Pin names in parentheses apply to 80C188EC 80L188EC Figure 20 Halt Cycle Waveforms 45 ...

Page 46: ...80C186EC 188EC 80L186EC 188EC 272434 20 Pin names in parentheses apply to 80C188EC 80L188EC Figure 21 Interrupt Acknowledge Cycle Waveforms 46 ...

Page 47: ...80C186EC 188EC 80L186EC 188EC 272434 21 Pin names in parentheses apply to 80C188EC 80L188EC Figure 22 HOLD HLDA Cycle Waveforms 47 ...

Page 48: ...80C186EC 188EC 80L186EC 188EC 272434 22 Pin names in parentheses apply to 80C188EC 80L188EC Figure 23 Refresh during HLDA Waveforms 48 ...

Page 49: ...272434 23 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EC 80L188EC Figure 24 READY Cycle Waveforms 49 ...

Page 50: ... the time required to fetch the opcode of the next instruction at the destination address All instructions which involve memory accesses can require one or two additional clocks above the mini mum timings shown due to the asynchronous hand shake between the bus interface unit BIU and exe cution unit With a 16 bit BIU the 80C186EC has sufficient bus performance to ensure that an adequate number of ...

Page 51: ...e Push All 0 1 1 0 0 0 0 0 36 68 POP e Pop Memory 1 0 0 0 1 1 1 1 mod 0 0 0 r m 20 24 Register 0 1 0 1 1 reg 10 14 Segment register 0 0 0 reg 1 1 1 regi01 8 12 POPA e Pop All 0 1 1 0 0 0 0 1 51 83 XCHG e Exchange Register memory with register 1 0 0 0 0 1 1 w mod reg r m 4 17 4 17 Register with accumulator 1 0 0 1 0 reg 3 3 IN e Input from Fixed port 1 1 1 0 0 1 0 w port 10 10 Variable port 1 1 1 0...

Page 52: ...a if we1 3 4 3 4 8 16 bit SBB e Subtract with borrow Reg memory and register to either 0 0 0 1 1 0 d w mod reg r m 3 10 3 10 Immediate from register memory 1 0 0 0 0 0 s w mod 0 1 1 r m data data if s we01 4 16 4 16 Immediate from accumulator 0 0 0 1 1 1 0 w data data if we1 3 4 3 4 8 16 bit DEC e Decrement Register memory 1 1 1 1 1 1 1 w mod 0 0 1 r m 3 15 3 15 Register 0 1 0 0 1 reg 3 3 CMP e Co...

Page 53: ... 1 0 0 0 w mod TTT r m 2 15 2 15 Register Memory by CL 1 1 0 1 0 0 1 w mod TTT r m 5an 17an 5an 17an Register Memory by Count 1 1 0 0 0 0 0 w mod TTT r m count 5an 17an 5an 17an TTT Instruction 0 0 0 ROL 0 0 1 ROR 0 1 0 RCL 0 1 1 RCR 1 0 0 SHL SAL 1 0 1 SHR 1 1 1 SAR AND e And Reg memory and register to either 0 0 1 0 0 0 d w mod reg r m 3 10 3 10 Immediate to register memory 1 0 0 0 0 0 0 w mod 1...

Page 54: ... 0 1 0 0 1 1 w 5a22n 5a22n SCAS e Scan string 1 1 1 1 0 0 1 z 1 0 1 0 1 1 1 w 5a15n 5a15n LODS e Load string 1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 w 6a11n 6a11n STOS e Store string 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 w 6a9n 6a9n INS e Input string 1 1 1 1 0 0 1 0 0 1 1 0 1 1 0 w 8a8n 8a8n OUTS e Output string 1 1 1 1 0 0 1 0 0 1 1 0 1 1 1 w 8a8n 8a8n CONTROL TRANSFER CALL e Call Direct within segment 1 1 1 0 1 ...

Page 55: ...E JG e Jump on not less or equal greater 0 1 1 1 1 1 1 1 disp 4 13 4 13 JNB JAE e Jump on not below above or equal 0 1 1 1 0 0 1 1 disp 4 13 4 13 JNBE JA e Jump on not below or equal above 0 1 1 1 0 1 1 1 disp 4 13 4 13 JNP JPO e Jump on not par par odd 0 1 1 1 1 0 1 1 disp 4 13 4 13 JNO e Jump on not overflow 0 1 1 1 0 0 0 1 disp 4 13 4 13 JNS e Jump on not sign 0 1 1 1 1 0 0 1 disp 4 13 4 13 JCX...

Page 56: ... e disp low sign extended to 16 bits disp high is absent if mod e 10 then DISP e disp high disp low if r m e 000 then EA e BX a SI a DISP if r m e 001 then EA e BX a DI a DISP if r m e 010 then EA e BP a SI a DISP if r m e 011 then EA e BP a DI a DISP if r m e 100 then EA e SI a DISP if r m e 101 then EA e DI a DISP if r m e 110 then EA e BP a DISP if r m e 111 then EA e BX a DISP DISP follows 2nd...

Page 57: ...g the presence of an A or B alpha character next to the FPO number or the absence of any alpha char acter The FPO number location is shown in Figures 4 5 and 6 REVISION HISTORY This data sheet replaces the following data sheets 272072 003 80C186EC 272076 003 80C188EC 272332 001 80L186EC 272333 001 80L188EC 272373 001 SB80C188EC SB80L188EC 272372 001 SB80C186EC SB80L186EC 57 ...

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