Intel 80386 Hardware Reference Manual Download

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Summary of Contents for 80386

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Page 5: ...inter 80386 HARDWARE REFERENCE MANUAL 1987...

Page 6: ...sion inteligent Identifier inteligent Programming Intellec Intellink iOSP iPDS iPSC iRMK iRMX iSBC iSBX iSDM iSXM KEPROM Library Manager MAPNET MCS Megachassis MICROMAINFRAME MULTIBUS MULTICHANNEL MUL...

Page 7: ...ersion of this publication for specific 80386 parameter values Detailed device specifications on 80386 family components can be found in the following publications 80387 Data Sheet Order Number 231920...

Page 8: ...usses techniques for connecting I O devices to an 80386 system Chapter 9 MULTIBUS I and 80386 This chapter describes the interface between an 80386 system and the Intel MULTIBUS I multi master system...

Page 9: ...4 3 1 2 Address Pipelining 3 5 3 1 3 32 Bit Data Bus Transfers and Operand Alignment 3 5 3 1 4 Read Cycle 3 10 3 1 5 Write Cycle 3 13 3 1 6 Pipelined Address Cycle 3 14 3 1 7 Interrupt Acknowledge Cyc...

Page 10: ...ocessor Interface 5 2 5 1 1 80287 Connections 5 2 5 1 2 80287 Bus Cycles 5 2 5 1 3 80287 Clock Input 5 4 5 2 80387 Numeric Coprocessor Interface 5 4 5 2 1 80387 Connections 5 4 5 2 2 80387 Bus Cycles...

Page 11: ...ysiS 6 28 CHAPTER 7 CACHE SUBSYSTEMS 7 1 Introduction to Caches 7 2 7 1 1 Program Locality 7 2 7 1 2 Block Fetch 7 2 7 2 Cache Organizations 7 3 7 2 1 Fully Associative Cache 7 3 7 2 2 Direct Mapped C...

Page 12: ...64 Interrupts 8 17 8 6 80286 Compatible Bus Cycles 8 17 8 6 1 AO A1 Generator 8 18 8 6 2 SO S1 Generator 8 18 8 6 3 Wait State Generator 8 19 8 6 4 Bus Controller and Bus Arbiter 8 20 8 6 5 82380 Int...

Page 13: ...3 Local Bus Extension iLBXTM II 10 4 Serial System Bus iSSB CHAPTER 11 PHYSICAL DESIGN AND DEBUGGING Page 9 11 9 11 9 14 9 14 9 14 9 16 9 17 9 17 9 18 9 19 9 20 10 1 10 1 10 2 10 4 10 6 10 7 10 7 11...

Page 14: ...ure Title Page 1 1 80386 System Block Diagram 1 2 2 1 Instruction Pipelining 2 1 2 2 80386 Functional Units 2 2 3 1 CLK2 and CLK Relationship 3 5 3 2 80386 Bus States Timing Example 3 6 3 3 Bus State...

Page 15: ...n and Implementation PAL Naming Conventions Bus Control Logic Bus Control Signal Timing 150 Nanosecond EPROM Timing Diagram 100 Nanosecond SRAM Timing Diagram 3 CLK DRAM Controller Schematic 3 CLK DRA...

Page 16: ...r MULTIBUS I Read Cycle Timing MULTIBUS I Write Cycle Timing Bus Priority Resolution Operating Mode Configurations Bus Select Logic for Interrupt Acknowledge Byte Swapping Logic Bus Timeout Protection...

Page 17: ...ransfers on 32 Bit Bus 3 13 3 5 Generation of BHE BLE and A1 from Byte Enables 3 23 3 6 Byte Enables during BS16 Cycles 3 23 3 7 Output Pin States during RESET 3 39 4 1 80386 Performance with Wait Sta...

Page 18: ...guides and COMMENTS Maga zine Basic support includes updates and the subscription service Contracts are sold in environments which repre sent product groupings i e iRMX environment CONSULTING SERVICES...

Page 19: ...System Overview 1...

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Page 21: ...ICROPROCESSOR The 80386 provides unprecedented performance At 20 MHz the 80386 is capable of executing at sustained rates of over five million instructions per second a speed comparable to that of mos...

Page 22: ...K GENERATOR CLK2 l 80386 80387 MICRO NUMERIC PROCESSOR COPROCESSOR A I V 80386 LOCAL BUS A v V 82385 82380 CACHE CACHE CONTROLLER DMA V V SYSTEM BUS A tj 7 V MEMORY PERIPHERALS G30107 Figure 1 1 80386...

Page 23: ...paging function simplifies the operating system swapping algorithms by providing a uniform mechanism for managing the physical structure of memory Task switching occurs frequently in real time multita...

Page 24: ...of the 80386 bus Other features of the 82380 are listed as follows High performance 32 bit DMA Controller 8 independently programmable channels 32 megabytes per second data transfer rate at 16 MHz 40...

Page 25: ...the 80386 and its support components The 82384 provides both the 80386 clock CLK2 and a half frequency clock CLK to indicate the internal phase of the 80386 and to drive 80286 compatible devices that...

Page 26: ...to perform multiple commands Data chaining to scatter data to separate memory locations separate pages for example and gather data from separate locations Automatic assembly and disassembly to convert...

Page 27: ...Internal Architecture 2...

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Page 29: ...ferent stages may overlap as illustrated in Figure 2 1 The six stage pipelined processing of the 80386 results in higher performance and an enhanced throughput rate over non pipelined processors The s...

Page 30: ...the 80386 and its environment It accepts internal requests for code fetches from the Code Prefetch Unit and data transfers from the Execution Unit and prioritizes the requests At the same time it gen...

Page 31: ...he Instruction Decode Unit takes instruction stream bytes from the Prefetch Queue and translates them into microcode The decoded instructions are then stored in a three deep Instruction Queue FIFO to...

Page 32: ...med by the Protection Test Unit The translated linear address is forwarded to the Paging Unit 2 6 PAGING UNIT When the 80386 paging mechanism is enabled the Paging Unit translates linear addresses gen...

Page 33: ...Local Bus Interface 3...

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Page 35: ...The address bus which generates 32 bit addresses consists of 30 address pins A31 A2 and four byte enable pins BE3 BEO Each byte enable pin corresponds to one of four bytes of the 32 bit data bus The...

Page 36: ...e up the inter face to an external numeric coprocessor BUSY and ERROR are status signals from the coprocessor PEREQ allows the coprocessor to request data from the 80386 The 80386 can use either the 8...

Page 37: ...h 0 Yes D C Data Control Indication High 0 Yes M IO Memory I O Indication High 0 Yes LOCK Bus Lock Indication Low 0 Yes AD8 Address 8tatus Low 0 Yes NA Next Address Request Low I 8 B816 Bus 8ize 16 Lo...

Page 38: ...6 inputs are sampled at CLK2 rising edges Many 80386 signals are sampled every other CLK2 rising edge some are sampled on the CLK2 edge when CLK is high while some are sampled on the CLK2 edge when CL...

Page 39: ...throughput without decreasing allowable memory or I 0 access time thus allowing high bandwidth with relatively inexpensive components In addition using pipelining to address slower devices can yield t...

Page 40: ...of two consecutive bytes and double words consist of four consecutive bytes However in the system hardware address space is implemented in four sections Each of the four 8 bit portions of the data bus...

Page 41: ...ta bus pins and byte enables This relationship holds for a 32 bit bus only the organization for a 16 bit bus is described later in Section 3 1 1O Data can be transferred in quantities of 32 bits 24 bi...

Page 42: ...KIt OUTPUT 00 031 INPUT DURING READ PIPELINED ClK2 INPUT BEon BE3 A2 A31 MIIOH DiCit WIR OUTPUTS ADSit OUTPUn NA INPUT READYH INPUT lOCK OUTPUT DO 031 INPUT DURING READ LOCAL BUS INTERFACE T1 T2 T1 T2...

Page 43: ...l BEO BE1 BE2 BE3 Figure 3 5 Consecutive Bytes in Hardware Implementation BED BEl BE2 BE3 BED BEl BE2 BE3 BED BYTE ADDRESS 0 1 2 3 4 5 6 7 8 WORD ADDRESS 0 0 2 2 4 4 6 6 8 131 24123 16115 81 7 BE3 BE2...

Page 44: ...386 operates on only bytes words and doublewords certain combinations of BE3 BEO are never produced For example a bus cycle is never performed with only BEO and BE2 active because such a transfer woul...

Page 45: ...CLE A31 A2 4 7 3 BE3 HIGH 6 SECOND BUS CYCLE A31 A2 7 3 DATA BUS BE3 LOW 6 32 BIT MEMORY BE2 HIGH 5 32 BIT MEMORY DATA BUS BE2 LOW 5 DATA BUS BEl LOW BEl HIGH Figure 3 7 Misaligned Transfer 3 11 4 4 D...

Page 46: ...E3 A2 A31 M IOH O C W R AD5 NA B516 READY LOCK IDLE T1 00 D31 LOCAL BUS INTERFACE CYCLE 1 NON PIPELINEO READ T1 T2 T1 CYCLE 2 NON PIPELINED READ T2 IDLE T2 T1 0 I Figure 3 8 Non Pipelined Address Read...

Page 47: ...truction is to be read Immediate data is included in an instruction LOCK is low if the bus cycle is a locked cycle In a read modify write sequence both the memory data read cycle and the memory data w...

Page 48: ...t the end of each wait state Once READY is sampled low the write cycle terminates If a new bus cycle is pending it begins on the next CLK cycle 3 1 6 Pipelined Address Cycle Address pipelining allows...

Page 49: ...2 A31 MIIO O C WIR AD5 NA B516 READY lOCK 00 031 IDLE T1 LOCAL BUS INTERFACE CYCLE 1 NON PIPELINED WRITE T1 T2 oun T1 CYCLE 2 NON PIPElINED WRITE T2 OUT2 T2 Figure 3 9_ Non Pipelined Address Write Cyc...

Page 50: ...elined cycle with at least one wait state Cycle 2 above 231630 20 Figure 3 10 Pipelined Address Cycles The first bus cycle after an idle bus state is always non pipelined_ To initiate address pipelin...

Page 51: ...the 80386 is enabled Interrupt acknowledge cycles are similar to regular bus cycles in that the 80386 bus outputs signals at the start of each bus cycle and an active READY terminates each bus cycle...

Page 52: ...cause each Interrupt Acknowledge bus cycle is followed by idle bus states asserting NA has no practical effect Choose the approach which is simplest for your system hardware design 231630 26 Figure 3...

Page 53: ...gned odd addressed 16 bit transfers BSI6 must be supplied by external hardware either through chip select decoding or directly from the addressed device BSI6 is sampled at the start of Phase 2 only in...

Page 54: ...le for this conversion Note that certain combinations of BE3 BEO are never generated When BSI6 is sampled active the states of BE3 BEO determine how the 80386 responds BSI6 has no effect if activated...

Page 55: ...OCAL BUS INTERFACE IDLE T1 CLK2 82384 CLK BEO BE1 BE2 BE3 A2 A31 M IO D C W R ADS NA BS16 READY LOCK 00 015 A TRANSFER REQUIRING TWO CYCLES ON 16 BIT DATA BUS CYCLE1A NON PIPELINED WRITE PART TWO T1 T...

Page 56: ...lining may be used as follows for these cycles BSI6 is not needed for cycles that use only DIS DO G BSI6 is not needed for a word aligned I6 bit write For write cycles all 32 bits of the data bus are...

Page 57: ...d when 00 07 of 16 bit bus is active BHE asserted when 08 015 of 16 bit bus is active A1 low for all even words A1 high for all odd words Key x don t care H high voltage level L low voltage level a no...

Page 58: ...cess times including address decoding time In a non pipelined address cycle this time is Four CLK2 cycles A31 A2 output delay maximum D31 DO input setup minimum 125 nanoseconds 38 nanoseconds 10 nanos...

Page 59: ...gnal Timing The amount of time from the output of valid address signals to the assertion of READY to end a bus cycle determines how quickly external logic must generate the READY signal READY must mee...

Page 60: ...se ADSO Figure 3 15 shows a typical circuit to connect the 82384 to the 80386 Either an external frequency source or a third overtone crystal can be used to drive the 82384 The FjC input indicates the...

Page 61: ...nals The phase of CLK can be used to make this determination ADS should be sampled on rising CLK2 transitions when CLK is high i e at the end of phase 2 see Figure 3 16 3 3 3 Crystal Oscillator Clock...

Page 62: ...QUALIFIER ClK ADS QUALIFIER Figure 3 16 Using ClK to Determine Bus Cycle Start 10 TO 30 OHM 32 000 MHZ OR 40 000 MHZ 8 CMOS OSCillATOR 47 OHM 4 K oF I 74F379 4 10 10 5 20 12 3D 13 40 9 CK 1 G TO 20 7...

Page 63: ...native method of generating CLK2 is to use a TTL oscillator coupled to a 74ACT244 buffer Although a typical 74ACT244 datasheet does not guarantee an output compatible with the 80386 CLK2 input some ma...

Page 64: ...ill not be interrupted by an incoming interrupt The incoming interrupt is an INTR request and the 80386 is programmed to ignore maskable interrupts The 80386 is automatically programmed to ignore mask...

Page 65: ...m the 80386 the 8259A appears as a set of I O ports accepts interrupt requests from devices connected to the 8259A determines the priority for transmitting the requests to the 80386 activates the INTR...

Page 66: ...cate that it intends to take control of the device the read cycle and write cycle should be locked to prevent another bus master from reading from or writing to the semaphore in between the two cycles...

Page 67: ...9 Error Condition Caused by Unlocked Cycles 3 5 3 LOCK Signal Duration G30107 The maximum duration of the LOCK signal affects the maximum HOLD request latency because HOLD is not recognized until LOCK...

Page 68: ...ol for transferring control of the local bus to other bus masters This protocol is implemented through the HOLD input and HLDA output 3 6 1 HOLD HLDA Timing To gain control of the local bus the reques...

Page 69: ...ASSERTED HOLD NEGAT O NO REQUEST T1 first clock of a non pipeltned bus cycle 80386 drives new address aod asserts ADS T2 subsequent clocks of a bus cycle when NA has not been sampled asserted in the c...

Page 70: ...HOLD is monitored to determine when the 80386 may regain control of the bus RESET takes precedence over the HOLD state An active RESET input will reinitialize the 80386 One NMI request is recognized a...

Page 71: ...initialization at least 80 CLK2 periods if self test is to be performed The CLK output of the 82384 is initialized with the rising edge of RESET When RESET goes low the 80386 adjusts the falling edge...

Page 72: ...heir DC and AC specifications_ The 80386 samples its ERROR input during Initialization to determine the type of proces sor extension present in the system_ This sampling occurs at some time at least 2...

Page 73: ...nquish bus control if it receives a HOLD request see Section 3 7 for a complete description of HOLD cycles Interrupt requests INTR and NMI are not recognized before the first instruction fetch Table 3...

Page 74: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 75: ...Performance Considerations 4...

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Page 77: ...stem performance The impact of memory device speed on performance is generally much greater than that of I O device speed because most programs require more memory accesses than I O accesses Therefore...

Page 78: ...e current bus cycle in most systems when the address has been latched the system can activate the 80386 NA input The 80386 outputs the address and status signals for the next bus cycle on the next CLK...

Page 79: ...e to execute a program than a 16 MHz 80386 operating with the same number of wait states The design and application determine whether frequency reduction makes sense In some instances a slight reducti...

Page 80: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 81: ...Coprocessor Hardware Interface 5...

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Page 83: ...addresses are automatically generated by the 80386 for coprocessor instructions and allow simple chip select generation using A31 high and M IO low Because A31 is high for coprocessor cycles the copro...

Page 84: ...M IO is always low A31 high The 80287 Command inputs CMDI and CMDO differentiate data from commands These inputs are connected to ground and the latched A2 output respectively The 80386 outputs addres...

Page 85: ...NPS2 CM01 CMDO 015 0 PEACK 80287 NUMERIC COPROCESSOR NPRO NPWR Figure 5 1 80386 System with 80287 Coprocessor Vee Vee G30107 data bus The 80386 automatically converts 32 bit memory transfers to 16 bit...

Page 86: ...y with the 80386 In the pseudosynchronous mode the interface logic of the 80387 runs with the clock signal of the 80386 whereas internal logic runs with a different clock signal 5 2 1 80387 Connection...

Page 87: ...LD A30 A3 INTR A2 80386 NMI WIR ADS 00 031 BUSY ERROR PEREa FROM OTHER PERIPHERALS 80387 CLOCK GENERATOR OPTIONAL WAIT STATE GENERATOR OPTIONAL AND OR LOGIC f r r r 32 5 2 80386 80387 PSEUDO SYNCHRONO...

Page 88: ...subsystem is only 16 bits wide the 80386 automatically performs the necessary conversion before transferring data to or from the 80387 Since the 80387 is a 32 bit device BSI6 must not be asserted duri...

Page 89: ...tion of the 80386 When the 80386 executes an ESC instruction that requires transfers of operands to or from the coprocessor the 80386 automatically sets an internal memory address base register memory...

Page 90: ...ocol of the 80287 Systems software can if necessary change the value of ET There are three reasons that ET may not be set 1 An 80287 is actually present 2 No coprocessor is present 3 An 80387 is prese...

Page 91: ...PX Note that we camot execute lAIl on 8086 88 if no 8087 is present test npx fninit Must use non wait form mov si offset dgroup terrp mav word ptr si 5ASAH Initial fze terrp to non zero vaLue fnstsw s...

Page 92: ...nd_387 set up for 387 exit code ends end start ds dgroup ss dgroup sst Figure 5 4 Software Routine to Recognize the 80287 Cont d 5 4 2 80387 Emulator G40107 The 80387 emulator circuit makes a lO MHz 8...

Page 93: ...rr n 8284A 1 CLKI I L Figure 5 5 80387 Emulator Schematic poa 14 1 01 13 02 D3 PDS 05 POS POS 06 P07 60 62 014 P01561 E 55 53 E 2 47 D26 45 42 39 II O F ERROR 18 ERRORt Vee7 VecS Vcc16 16 Vcc2S 25 Vcc...

Page 94: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 95: ...Memory Interfacing 6...

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Page 97: ...placed in fast memory and all other functions are placed in slow memory high performance for most operations can b achieved at a cost significantly less than that of a fast memory subsystem For examp...

Page 98: ...vices Many design examples in this manual use PAL Programmable Array Logic devices which can be programmed by the user to implement random logic A PAL device can be used as a state machine or a signal...

Page 99: ...e AND gate Programming a PAL device consists of determining where the XS must be placed in the AND array This task is simplified by the use of a PAL assembler program Such a program accepts input in t...

Page 100: ...the address decoder which converts the 80386 address into chip select signals is located before the address latches In general the decoder may also be placed after the latches If it is placed before...

Page 101: ...devices are slow to remove read data from the data bus after a read cycle If a write cycle follows a read cycle the 80386 may drive the data bus before a slow device has removed its outputs from the b...

Page 102: ...errupt acknowledge cycles generate the Interrupt Acknowledge INTA output which is returned to the 8259A Interrupt Controller The second INTA cycle commands the 8259A to place the interrupt vector on t...

Page 103: ...MEMORY INTERFACING N I 0 Ai i e It 113 I I 0 I 113 N I 0 e I 12 I o 8 0 I 113 I j II I 0 0 0 0 0 0 0 0 r I I I I I I I Ii l wt l t t ttT o 0 I I g I I 12 Cl I ll i i I 6 7...

Page 104: ...FCf J U ADS l JJ U JJ I LJJ l JJ ADDR xt xt rtf DATA If READ READ READ WRITE READ SEL 1 fJJ f JJ UJ J ALE 1 00 h r h In n DEN I iLr I 1 r II MRDC I 1 1 II II MWTC 1 J NA U IU U IU u READY LJ IL V LV I...

Page 105: ...ulated from the waveforms in Figure 6 6 In the following example the timings for I O accesses are calculated for CLK2 32 MHz and B series PALs All times are in nanoseconds Check the most recent 80386...

Page 106: ...NED 1 2 3 4 1 2 3 1 2 3 1 2 3 4 1 2 3 4 1 2 3 4 U UCfC U fCfIfC U Cf fUIfCf fU fU t fU1 lW lW rr D W llD u W rftf rJ tj rtJj m XY I XX j YJjJ ff I READ READ READ WRITE READ READ I fJJfJfJ XY I XX h lr...

Page 107: ...input of each SRAM device is connected to the MRDC signal from the bus controller the WE input of each SRAM device is driven by the MWTC signal Because it is possible to write to only some bytes of a...

Page 108: ...Itt 1m IXXYXXIXXYXX DATA XX XXXX mxx xx YJ rtU X xm IXXXX mx mxx xm READ READ WRITE REfD READ READ SEL XX I IX IXXlX I xx IBmrxmm I tI I I ffI 1 if Y I ri xxn NONE SELECTED en 1 I ALE In In In V v II...

Page 109: ...7 nanoseconds This is acceptable because latched addresses are held for at least as long as the end of the bus cycle tWA Address hold after Write MWTC rise 1 x CLK2 period PAL RegOut Max PAL RegOut Mi...

Page 110: ...nd all code prefetches from the EPROMs are slower requiring two bus cycles instead of one However this reduction is acceptable in certain applications A system that uses EPROMs only for power on initi...

Page 111: ...ltiple banks so that adjacent addresses are in different banks the DRAM precharge time can be avoided for most accesses With two banks of DRAMs one for even 32 bit doubleword addresses and one for odd...

Page 112: ...he DRAMs to precharge before starting the access address pipelining does not speed up the same bank cycle the number of wait states is identical with or without address pipelining The numbers in Table...

Page 113: ...most significant byte D31 D24 Each of the 32 data lines of the 80386 are connected to one DRAM chip from each bank If Nx1 DRAMs are used the corresponding data line is connected to both the Din and D...

Page 114: ...ONTROL CLK PAL l6RSe eso AOWSEL ROWSEL DEN Cs1 MUXOE DISABLE CTiIt C53 DRAM STATE PAL 1liR8B Cs CS2 A2 RAsa RFRO RAS1 I I 41 r CLOCK DE REFRESH ADDRESS COUNTER PAL laRS A7 0 0 SOL 11 MULTIPLEXED ADDRE...

Page 115: ...l of the following conditions exist at once o MjIO WjR and DjC outputs of the 80386 indicate either a memory read memory write or code fetch o The bus is idle or the current bus cycle is ending READY...

Page 116: ...v V V V V Iv V ADS XX It n n n w JJl n IXXY SELECT ROWSEL r h ADDR I y I I ROW COLUMN ROW COLUMN ROW COLUMN REFRESH RASO RAS1 1 C1I CASx I I Ir I LOW ONLY FOR ENABLED BYTES 0 WC WE DATA DEN R r t READ...

Page 117: ...CAS signals are registered externally the BE3 BEO lines must be latched externally so that the DRAM Control PAL inputs maintain the valid byte enables For the 2 CLK design the RAS and CAS signals are...

Page 118: ...L l6RSB HROWSEL HOISABLE CLOCK OE REFRESH ADDRESS COUNTER PAL WE 1 1 DEHt DT R II0 0 co c L J W EIGHT 256K 1 DRAMs 1 0 SEL p I I I MULTIPLEXED ADDRESS A20 12I ROW ADDRESS V V L L Al1 3 I COLUMN ADDRES...

Page 119: ...drives only 16 DRAMs Because internal registers have a greater maximum delay time and potentially less drive the choice between registered PALs or external registers affects all of the DRAM timing par...

Page 120: ...XYJ SELECT ROWSEL L U r LU n I L L I L W ADDR XJ JJ J JJIXAXXXX X X X X X X X xxx fXXXX RASO ROW COLUMN ROW COLUMN ROW COLUMN I COLUMN Ir REFRESH RAS1 a I I CASx j WE Ir I 1 11 L LOW ONLY FIR EN BLED...

Page 121: ...er the refresh cycle is complete the Refresh Address Counter PAL increments so that the next refresh cycle refreshes the next sequential row The frequency of refreshing and the number of rows to be re...

Page 122: ...executed during this time The 3 CLK and 2 CLK designs can be modified for burst refreshes by lengthening the maximum count of the Refresh Interval Counter to cover a 4 millisecond interval and holdin...

Page 123: ...he 82380 DRAM Refresh Control to perform refresh the Refresh Interval Counter PAL and the Refresh Address Counter PAL can be eliminated 6 3 6 Initialization Once the system is initialized the integrit...

Page 124: ...is The DRAM design 2 CLK or 3 CLK for six combinations of DRAM speed and CLK frequency is listed in the Table 6 3 The table also indicates for each DRAM type whether data transceivers and or external...

Page 125: ...Cache Subsystems 7...

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Page 127: ...te every bus cycle in 100 nanoseconds Faster static RAMs SRAMs can meet the bus timing requirement but they offer a relatively small amount of memory at a higher cost Large SRAM systems can be prohibi...

Page 128: ...inciple is known as program locality or locality of reference Program locality makes cache systems possible The same concept on a larger scale allows demand paging systems to work well In typical prog...

Page 129: ...st 7 2 CACHE ORGANIZATIONS 7 2 1 Fully Associative Cache Most programs make reference to code segments subroutines stacks lists and buffers located in different parts of the address space An effective...

Page 130: ...parison is needed to determine whether requested data is in the cache The many address comparisons of the fully associative cache are necessary because any block from the main memory can be placed in...

Page 131: ...386 address are decoded to select the cache subsystem from among other memories in the memory space The direct mapped cache organization is shown in Figure 7 3 32 BIT PROCESSOR ADDRESS INDEX TAG FFFC...

Page 132: ...cessor in the example above makes frequent requests for locations 12FFE8H and 44FFE8H the controller must access the main memory frequently because only one of these locations can be in the cache at a...

Page 133: ...87654321 13579246 f4 32 BITS j 16 MEGABYTE DRAM Figure 7 4 Two Way Set Associative Cache Organization TAG IF 00 00 G30107 The set associative cache however is more complex than the direct mapped cach...

Page 134: ...situation shown in Figure 7 5 could occUr The following sections describe the write through and write back methods of updating the main memory during a write operation to the cache 7 3 1 Write Through...

Page 135: ...than the corresponding data in the main memory Before overwrit ing any block in the cache the cache controller checks the altered bit If it is set the control ler writes the block to main memory befor...

Page 136: ...systems for example another stale data problem is introduced If new data is written to main memory by one device the cache maintained by another device will contain stale data A system that prevents t...

Page 137: ...e reduction in the hit rate caused by non cacheable memory by using the string move instruction REP MOVS to copy data between non cacheable memory and cacheable memory and by mapping shared memory acc...

Page 138: ...al mainframe traces and selecting the one which produced the lowest hit rate Thus the numbers listed are a conservative estimate of cache efficiency Note that hit rate statistics are not absolute quan...

Page 139: ...in a discrete cache design the 82385 integrates this function and performs zero waitstate bus watching The overall memory bandwidth is increased since the 80386 can access its cache at the same time a...

Page 140: ...ne must weigh the additional cost against the additional performance The cache in this example stores both code and data rather than only code Code only caches are easier to implement because there ar...

Page 141: ...th the tag information stored in the cache to deter mine of the block in the cache is the block needed by the 80386 a If the tag matches the 80386 either reads the data in the cache or writes new data...

Page 142: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 143: ...fO Interfacing 8...

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Page 145: ...egisters The first 256 bytes of the I O space are directly addressable The entire 64 kilobyte I O space is indirectly addressable through the DX register Memory mapping offers more flexibility in prot...

Page 146: ...needed 8 2 2 8 Bit I O Eight bit I O devices can be connected to any of the four 8 bit sections of the data bus Table 8 1 illustrates how the address assigned to a device determines which section of t...

Page 147: ...BE3n BE2n BE1n BEOn 1 0 INTERFACING DEn DEn DEn DECODE Figure 8 1 32 Bit to 8 Bit Bus Conversion 8 3 8 BIT 110 DeVICE G30107...

Page 148: ...irectly to I O device selects as shown in Figure 8 2 8 3 BASIC 110 INTERFACE In a typical 80386 system design a number of slave I O devices can be controlled through the same local bus interface Other...

Page 149: ...tems the same control logic address latches and data buffers can be used to access both memory and I O devices The schematic of the interface is shown in Figure 8 4 and described in the following sect...

Page 150: ...the address Therefore the number of address latches needed is determined by the location of the address decoder as well as the number of address bits and chip select signals required by the interface...

Page 151: ...A 2 INTERRUPT CONTROLLER iNTA A2 AD 01 0 07 0 Figure 8 4 Basic 1 0 Interface Circuit 1 M OE 2K aSRAM o AIG O 107 0 IR1 O I l is 1_ M DE 21 aSRAM o AIG O 107 1 21128 16K aEPROM AilO 07 0 82C 2 TIMERI C...

Page 152: ...the transceiver outputs This signal is generated by the bus control logic Note that in a system using the 82380 the data transceivers must be disabled whenever the 80386 performs a read access to one...

Page 153: ...s to a relatively small delay Typically I O devices are used infrequently enough that the access time is not critical 8 4 TIMING ANALYSIS FOR 1 0 OPERATIONS In this section timing requirements for dev...

Page 154: ...es PALs All times are in nanoseconds tAR Address stable before Read IORC fall tAW Address stable before Write IOWC fall 5 x CLK2 period PAL RegOut Max Latch Enable Max PAL RegOut Min 5 x 31 25 12 11 5...

Page 155: ...Jif J Y ifff V1 J E F CfCfif S II II II S C If U J V ADS I I l l J l r Ll lIr1J lIr1J ADDR JJ JJ till till YJ X XXX DATA Y READ READ READ en SEL Xi X J XXX X ALE I A In DEN II II L Ii lORD II II lown...

Page 156: ...80386 Data Setup Min 12 11 5 6 10 335 5 nanoseconds tRD Data delay from Read IORC 9 x CLK2 period PAL RegOut Max xcvr prop Min 80386 Data Setup Min 9 x 31 25 12 6 10 253 25 nanoseconds tDF read IORC r...

Page 157: ...such accesses justifies Therefore the preferred solution is to delay all I 0 cycles by the minimum recovery time Because most I 0 accesses are relatively infrequent performance is not degraded The I 0...

Page 158: ...nnels and can serve as a high performance replacement for two 8251A Universal Synchronous Asynchronous Receiver Transmitters USARTs Figure 8 6 shows connections from the basic I O interface through wh...

Page 159: ...two consecutive interrupt acknowledge cycles 8 5 2 1 CASCADED INTERRUPT CONTROLLERS TO THE 82380 PIC Each of the external requests of the 82380 PIC can be cascaded with one slave 82C59A Interrupt Cont...

Page 160: ...ck to back interrupt acknowledge cycles as described in Chapter 3 The 8259A timing requirements are as follows Each interrupt acknowledge cycle must be extended by at least one wait state Wait state g...

Page 161: ...r 9 describes the interface to slave controllers that reside on a MULTIBUS I system bus 8 5 3 3 HANDLING MORE THAN 64 INTERRUPTS If an 80386 system requires more than 64 interrupt request lines a thir...

Page 162: ...ts from 80386 BEO BE3 outputs Address decoder Determines the device the 80386 will access Address latches Connect directly to 80386 address pins A19 A2 and the outputs of the AO Al generator Data tran...

Page 163: ...t state generator PAL shown in Figure 8 11 controls the READY input of the 80386 For local bus cycles the wait state generator produces signal outputs that correspond to each wait state of the 80386 b...

Page 164: ...non occurring pattern of Byte Enables either none are asserted or the pattern has Byte Enables asserted for non contiguous bytes To meet the READY input hold time requirement 25 nanoseconds for the 8...

Page 165: ...he 82380 is designed for easy interface to the 80386 processor It consists of a set of signals to interface directly to the 80386 local bus Figure 8 13 depicts a typical system configura tion with the...

Page 166: ...WS2 __ Figure 8 10 SO S1 Generator Logic r J o WSI J Q K 16R8 ADSO ClK 82288 ALE 1 ClK Y PCLK CHIP SELECT FOR 80286 COMPATIBLES Figure 8 11 Wait State Generator Logic 8 22 SOH THESE OUTPUTS SHOULD BE...

Page 167: ...memory and an I 0 device typically a magnetic disk or communications channel without intervention from the 80386 Shifting the I O processing function from the 80386 to the 82258 improves overall syst...

Page 168: ...terface Auto assembly and disassembly to convert from l6 bit memory to 8 bit I O or vice versa Compare translate and verify functions The option to use one Of the four high speed channels as a lower s...

Page 169: ...owledge HLDA pins on both the 80386 and the 82258 facili tate the transfer of bus control between the 80386 and the 82258 Figure 8 14 shows the logic to transfer bus control When the 82258 needs bus a...

Page 170: ...2258 is achieved indirectly through memory the 80386 occasionally performs bus cycles to the 82258 For example the 80386 performs a direct access to set the general mode register during initialization...

Page 171: ...CPU shared memory a Serial Interface Unit a transceiver and a LAN link see Figure 8 16 The 82586 performs all functions associated with data transfer between the shared memory and the LAN link includi...

Page 172: ...s in a high performance high cost interface The CPU typically an 80186 an 80188 or a microcontroller executes the data link layer a functional division of software and sometimes the network transport...

Page 173: ...ed SRAM is shared the 82586 cannot access the 80386 core memory The 80386 and 82586 operate in parallel except when both require access to the SRAM In this instance one processor must wait while the o...

Page 174: ...o the DMA transfer Through the buffer chaining feature of the 82586 the header information can be directed to a separate buffer as long as the minimum buffer size requirements are met 8 6 7 4 Shared B...

Page 175: ...1 0 INTERFACING G30107 Figure 8 19 Shared Bus Interface 8 31...

Page 176: ......

Page 177: ...MULTIBUS I and 80386 9...

Page 178: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 179: ...mining which resources to share between all processors and which to keep for only one processor s use These choices affect system relia bility integrity throughput and performance The deciding factors...

Page 180: ...address bits from 80386 BEO BE3 outputs Address decoder Determines whether the bus cycle requires a MULTIBUS I access MULTIBUS I address latches Connect directly to 80386 address pins A23 A2 and the...

Page 181: ...BUS ADDRESS LATCH ADDRESS DECODER Y A DATA MULTIBUS DATA 80386 DATA TRANSCEIVER I SO S1 80386 STATUS LOGIC t 82288 BUS CONTROLLER WAIT STATE GENERATOR I 82289 BUS ARBITER Figure 9 1 80386 MULTIBUS I I...

Page 182: ...he MULTIBUS I latches The ALE output of the 82288 latches the 80386 address for the MULTIBUS I as shown in Figure 9 2 Inverting latch transceivers are needed to provide active low MULTIBUS I data bits...

Page 183: ...ts BSI6 and MBEN A25 A24 A23 A22 A2l A20 A19 A18 I O resources residing on MULTIBUS I can be memory mapped into the memory space of the 80386 or I O mapped into the I O address space independent of th...

Page 184: ...s READY to be output between two and three CLK cycles after ARDY goes active The PCLK signal which is necessary for producing 80286 compatible wait states is gener ated by dividing the CLK signal from...

Page 185: ...are shown in Figures 9 5 and 9 6 The only differences between the timings are that a read cycle controls the data latch transceivers using RD and outputs the MRDC command signal whereas a write cycle...

Page 186: ...0 I 00 CPURD MBALE MBADDR BHE DATA XACK READY ENDCYC2 W Lf u 1 J1 JUU 1 J1 JUU 1 J1 JUUh n n J _ LSj U LJL JLJU j t _ wI w r _ t 1 1 J t t I 1 n t i t 4 J D _ lV rr T V G30107 Figure 9 5 MULTIBUS I Re...

Page 187: ...I I I I MBALE I I I I MBA BHE I i DATA I I XACK i I I READY I I I I ENDCYCZ I I I I I I I Ts Tc Tc 3Tcs MINIMUM ru uru uru uru uru uILri rf U UjU L JL JUl I t 1 7 H Figure 9 6_ MULTIBU5 I Write Cycle...

Page 188: ...ystems contend for the use of shared resources If one processor requests access to MULTIBUS I while another processor is using it the requesting processor must wait Bus arbitration logic controls acce...

Page 189: ...iority technique requires external logic to recognize the BPRN inputs from all bus arbiters and return the BPRO signal active to the requesting bus arbiter that has the highest priority The number of...

Page 190: ...inter MULTIBUS I AND 80386 SERIAL PRIORITY RESOLVING TECHNIQUE 74148 PRIORITY ENCODER PARALLEL PRIORITY RESOLVING TECHNIQUE Figure 9 7 Bus Priority Resolution 9 12 74138 3 T08 DECODER 4 210760 132...

Page 191: ...e depends on how often a subsystem accesses MULTIBUS I and how this frequency compares to that of the other subsystems o Mode 1 is adequate for a subsystem that needs MULTIBUS I access only occasional...

Page 192: ...he four modes mentioned above Locked MULTIBUS I cycles are typically used to implement software semaphores described in Chapter 3 for critical code sections or critical real time events Locked cycles...

Page 193: ...sits cascade address pins CASO CASl CAS2 to select that slave controller During the second cycle the 80386 reads an 8 bit vector from the selected interrupt controller and uses this vector to service...

Page 194: ...errupt Acknowledge 9 5 2 Byte Swapping during MULTIBUS I Byte Transfers The MULTIBUS I standard specifies that all byte transfers must be performed on the lower eight data lines MULTIBUS I DATO DAT7 r...

Page 195: ...tivates a one shot that outputs a I millisecond pulse The rising edge of the pulse activates the TIMEOUT signal if READY does not go active within 1 millisecond to clear the TIMEOUT flip flop The TIME...

Page 196: ...4 BUS CONTROL _ MULTIBUS BHEN _ MULTIBUS ADRO G30107 The iLBX Local Bus Expansion is a high performance bus interface standard that permits the modular expansion of an 80386 based system An iLBX inter...

Page 197: ...yed to allow adequate setup time for BHEN In this example the WS2 signal which is active during the third CLK cycle of the 80386 bus cycle provides the delay A chip select output of address decoding l...

Page 198: ...sing subsystems need not use the same address mapping for dual port RAM The disadvantage of dual port RAM is that its design is more complex than that of either local or system memory Dual port RAM re...

Page 199: ...accessing dual port RAM The 80386 cannot gain control of MULTIBUS I to complete the locked operation and the other device cannot relinquish control of MULTIBUS I because it cannot complete its access...

Page 200: ......

Page 201: ...MULTIBUS II and 80386 10...

Page 202: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 203: ...a low cost serial system bus and full multi processing support MULTIBUS II achieves these features through five specialized Intel buses Parallel System Bus iPSB Local Bus Extension iLBX II Serial Syst...

Page 204: ...es implementing the message space and the inter connect space as well as devices in the memory space and the I O space Three types of bus cycles define activity on the iPSB bus Arbitration Cycle Deter...

Page 205: ...o I U ARBITRATION CYCLE I TRANSFER CYCLE EXCEPTION CYCLE Figure 10 1 iPSB Bus Cycle Timing f G30107 t 3 c r til C en l Z C Xl o U Xl m...

Page 206: ...tion The BAC and MIC are implemented in Intel gate arrays In addition Intel is developing an advanced CMOS device the Message Passing Coprocessor MPC that integrates the functions of the BAC and the M...

Page 207: ...on the multiplexed address and data bus AD31 ADO and sets the Parity inputs PAR3 PARO accordingly Other iPSB signals are Reset RST Reset Not Complete RSTNC and ID Latch LACHn n slot number These signa...

Page 208: ...hough the MIC gains access to the iPSB bus through the BAC the MIC drives the address data bus directly As a requesting agent the MIC drives the address and data at the appropriate times As a receivin...

Page 209: ...primary requesting agent initializes and configures all other bus agents 10 4 SERIAL SYSTEM BUS iSSB The Serial System Bus iSSB provides a simple low cost alternative to the Parallel System Bus iPSB...

Page 210: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 211: ...Physical Design and Debugging 11...

Page 212: ......

Page 213: ...output valid delays will increase if these loadings are exceeded The addressing pattern of the software can affect I O power by changing the effective frequency at the address pins The variation in f...

Page 214: ...ors are on for a short time when the output is switching This increased load causes a negative spike on Vee and a positive spike on ground In synchronous systems in which many gates switch simul taneo...

Page 215: ...require less total board space They should be connected as in Figure 11 3 Leaded capaci tors can also be used if the leads are kept as short as possible Six leaded capacitors are required to match the...

Page 216: ...w level before reflections have time to dissipate and overshoot and undershoot occur There are two methods of termination series and split A series termination compensates for excess current before th...

Page 217: ...wn by R1 and R2 11 2 2 Interference Interference is the result of electrical activity in one conductor causing transient voltages to appear in another conductor Interference increases with the followi...

Page 218: ...s exists The bus is on an external layer of the board The bus is on an internal layer but not sandwiched between power and ground planes that are at most 10 mils away Avoiding closed loops in signal p...

Page 219: ...2384 is designed to match 80386 specifications Terminating the CLK2 output with a series resistor to obtain a clean signal The resistor value is calculated by measuring the total capacitive load on th...

Page 220: ...TERS THICKNESS DIELECTRIC CONSTANT DISTANCE TO GROUNDIVcc PLANES TERMINATION RESISTOR MUST BE LOW INDUCTANCE TYPE RECOMMEND CARBON FILLED TYPE G30107 Figure 11 8 CLK2 Series Termination where Tj junct...

Page 221: ...ambient temperature because the measurement is localized to a single point top center of the package o The worst case junction temperature T is lower when calculated with case temperature for the fol...

Page 222: ...eral valuable debugging concepts and useful hints Use these guidelines in conjunction with the 80386 data sheet which contains detailed information about the 80386 11 5 1 Hardware Debugging Features E...

Page 223: ...low memories or peripherals Wait state requirements are a function of the device being addressed Therefore the address decoder must determine how many wait states if any to add to each bus cycle The a...

Page 224: ...address of the code segment is set internally to FFFFOOOOH Therefore the physical address of the first code fetch after reset is always FFFFFFFOH The simple diagnostic program must begin at this loca...

Page 225: ...PROMs Now the simple debug program described above can be run to see whether the parts of the system work together After installing the EPROMs the READY line should be tied high negated so that the 80...

Page 226: ...rks The program is short 45 bytes to be easily understood Because it is short and because it loops continuously a logic analyzer or even an oscilloscope can be used to observe system activity This pro...

Page 227: ...ORCE CPU TO BREAK PRE FETCH QUEUE AND FETCH THE NEXT INSTRUCTION AGAIN THIS PREVENTS THE RAM DATA WRITTEN FROM JUST LINGERING ON THE DATA BUS UNTIL THE READ OCCURS READ DATA FROM RAM ADDR 0 AND 1 AND...

Page 228: ...73 IOV ax 5473H F009 C7 47 02 2961 MOV BX 2 2961H FOOE EB 01 90 JMP READ Fall 81 3F 5473 READ CMP BX 5473H F015 75 00 JNE BADRAM F017 81 7F 02 2961 CMP BX 2 2961H FDIC 75 06 JNE BADRAM FOIE BO AA MOV...

Page 229: ...also work If the shutdown LED comes on and the 80386 stops running the data being read in during code fetch cycles is garbled The programmer should check the EPROM contents the wiring of the address...

Page 230: ......

Page 231: ...Test Capabilities 12...

Page 232: ......

Page 233: ...grammable Logic Arrays PLAs the Entry Point Control and Test PLAs and the contents of its Control ROM CROM The automatic self test is initiated by setting the BUSY input active during initialization a...

Page 234: ...tion Random access memory RAM holds the 32 physical addresses upper 20 bits only that correspond to the linear addresses in the CAM Logic implements the four way cache and includes a 2 bit replacement...

Page 235: ...n to the TLB through the data register The two test operations that may be performed on the TLB are Write the physical address contained in the data register and the linear address and tag bits contai...

Page 236: ...he TLB is to receive write data Its value is changed according to a proprietary algorithm after every TLB hit For testing a TLB write may use the replacement pointer value that exists in the TLB or it...

Page 237: ...ins are effectively removed from their circuits This state is accomplished through the HOLD and HLDA pins When the HOLD input of the 80386 is asserted the 80386 places all of its outputs except for HL...

Page 238: ......

Page 239: ...Appendix Local Bus Control PAL Descriptions A...

Page 240: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 241: ...e PALs the choice of PALs is currently limited to only 20 pin B series PALs PAL 1 FUNCTIONS PAL l is implemented as two main state machines The BUSSTATE state machine which is used to follow the 80386...

Page 242: ...enable DT R is simply a latched version of W R This saves a PAL output and also guarantees that the transceiver direction does not change while DEN is enabled PAL EQUATIONS The equations for PAL I an...

Page 243: ...us cycle not to the local bus state definitions for SEQUENCE local cycle sequence counter SEQO SEQI SEQ2 SEQ3 II Pin names CLK ADS READY WR CSOWS CSIWS CSIO RESET CLK2 OE NA IDLE PIPE L2 Ll La Ql QO B...

Page 244: ...then go ACTIVE unused state should never occur if entered upon power up go IDLE 11 1111 111111 1 1 111 11 n IIIIIIIIIIIIIIII I I I IIIIIII 1111111 1111 1 1111111111111 state_diagram LOCALSTATE state...

Page 245: ...I II II IIIII IIII II III nlln state_diagram SEQUENCE counter for LOCALSTATE state SEQ3 if RESET then SEQO else if CLK then SEQ3 else SEQ2 state SEQ2 if RESET then SEQO else if ICLK then SEQ2 else SEQ...

Page 246: ...L L x H L L H H NOTLOCAL L NA activated externally c H L H H x x x x NOTLOCAL L c L L x L x x x x NOTLOCAL L c H L L L x x x x SAMPLECS L non local c L L x H x H H H NOTLOCAL L c H L H H x x x x NOTLO...

Page 247: ...L 1I150nS SRAM read e L L x H L H L H MEMORY L e H L H H x x x x MEMORY H e L L x H x x x x MEMORY H e H L L H x x x x MEMORY L e L L L L x x x x FLOAT L e H L H L x x x x FLOAT L e L L H H x x x x W...

Page 248: ...H NOTLOCAL L NA activated externally c H L HtH x x x x NOTLOCAL L c L L x L x X X X NOTLOCAL L c H L L Lt x x x x SAMPLECS L peripheral write c L L x H H H H L CMOOELAY L c H L H H H x x x 10 L c L L...

Page 249: ...pin 9 pin 1 pin 11 pin 19 pin 18 pin 17 pin 16 pin 15 Input pins 82384 CLK 80386 M IO 80386 D C 80386 W R local cycle state from PAL 1 local cycle state from PAL 1 local cycle state from PAL 1 chip se...

Page 250: ...O LOCALSTATE MEMORY LOCALSTATE FLOAT LOCALSTATE NOTLOCAL IOWC LOCALSTATE WAITING LOCALSTATE SAMPLECS LOCALSTATE CMDDELAY LOCALSTATE IO LOCALSTATE ENDIO LOCALSTATE MEMORY LOCALSTATE FLOAT LOCALSTATE NO...

Page 251: ...vectors CLK2 CLK LOCALSTATE MIO DC WR CSOWS MRDC MWTC IORC IOWC INTA ALE DEN RDY inputs outputS C C M D W L L I C R K K LCCALSTATE 0 2 c L c H c L c H e L c H c L c H c L c H c L c H e L c H c L c H c...

Page 252: ...H H c H MEMORY H H L xl L H H H H L L H c L MEMORY x x x x L H H H H L L H c R MEMORY X X x xl L H H H H L L L e L MEMORY X X X xl L H H H H L L L c R FLOAT x x x x H H H H H L H H e L FLOAT X X X x H...

Page 253: ...H L H Hj WAITING x x x Xj H H H H H H H Hj WAITING x x x Xj H H H H H H H Hj WAITING x x x xj H H H H H H H Hj peripheral interrupt ack SAMPLECS X X X Hj H H H H H L H Hj CMOOELAY X X X xj H H H H H...

Page 254: ...SET Ll L2 READY RESET LO Ll L2 QO RESET LO Ll RESET CLK CSOWS CSlWS CSIO IDLE LO Ll L2 RESET Ll RESET CLK LO Ll LO Ll READY CSlWS Ll L2 LO Ll L2 LO L2 QO Ql LO Ll QO Ql CLK CSOWS CSlWS CSIO IDLE LO L2...

Page 255: ...csows DC flO Ll l2 MIO WR DC DEN flO Ll MIO WR DC DEN Ll Il2 MIO WR IOWC IOWC lO Ll l2 IOWC flO Ll ROY IOWC lO l2 ROY csows DC flO Ll l2 MIO WR DC DEN flO Ll M 10 WR DC DEN Ll Il2 MIO WR INTA INTA flO...

Page 256: ...I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I...

Page 257: ...Appendix 80387 Emulator PAL Description B...

Page 258: ......

Page 259: ...S PAL MATH CYCle MATHCYC INTeL Corporation IRDY A31 LRESET lADS MIO IRD IAVALID IDVALID ICLK16 GND TP2 ICLK16D IREADYO IDVALIDD IAVALIDD NC IIORDD IIOWCD IREADYOD VCC IF TP2 AVALIDD ADS RDY ILRESET CL...

Page 260: ......

Page 261: ...Append DRAM PAL Descriptions...

Page 262: ......

Page 263: ...ld times cannot be guaranteed no hazards exist DRAM STATE PAL The DRAM State PAL determines when to run a new DRAM cycle and tracks the state of the DRAM through the cycle The inputs sample DRAM reque...

Page 264: ...4 DT R DRAM CONTROL Indicates write read Start Of Phase on PAL DT R out Used only in 2 ClK 2nd ClK of access A2 System Address Selects one of the two DRAM Start Of Phase in bit 2 banks which DRAM acce...

Page 265: ...CLK ROWSEL QO QI CLK ROWSEL QI QO CLK ROWSEL QI CLK CSO CSI CS2 CS3 CS4 MUXOE A2 A2REG ROWSEL QI CLK CSO CSI CS2 CS3 CS4 MUXOE A2 A2REG ROWSEL QI QO CLK CSO CSI CS2 CS3 CS4 MUXOE ROWSEL QI QO CLK DRA...

Page 266: ...RGE no dram request pending H H H H H L L H PRECHARGE2 wait for precharge H L L H L L H H ACCESSl start DRAM cycle to other bank L L L H L L L H ACCESS2 continue DRAM cycle L L H H L L L H ACCESS3 con...

Page 267: ...L L H H X ACCESS4 continue refresh cycle L H H L L H H X ACCESSS continue refresh cycle H H L L L H H X ACCESS6 cant i nue refresh cycle H H H H H H H X PRECHARGE can t start refresh precharge H H H H...

Page 268: ...E RAS corresponding to A2 I I IRASl A2REG MUXOE or refresh I I A2REG A2REG maintain state of sampled A21 I MUXOE MUXOE maintain MUXOE state I 1 I I always v 1 I state ACCESS4 011l fourth cycle of acce...

Page 269: ...MUX MUXOE 111 MUX MUX M R M R MUXOE RFRQ 10 1 MUX MUX RFR RFR RFRQ RO SEl QO Q1 ClK 00 01 11 10 A2REG 00 1 A2R A2R key 01 1 A2R A2R IA2R A2 A2 111 A2R A2R A2R A2R A2REG 10 1 A2R A2 A2 ROWSEl QO Q1 Cl...

Page 270: ...O CLK ROWSEL QI CLK CSO CS1 CS2 CS3 MUXOE A2 A2REG ROWSEL Q1 CLK CSO CS1 CS2 CS3 MUXOE A2 A2REG ROWSEL Q1 QO CLK CSO CS1 CS2 CS3 MUXOE ROWSEL Q1 QO CLK DRAMSElECT MUXOE ROWSEL Q1 QO CLK MUXOE RFRQ RAS...

Page 271: ...HHHLHX H L H H H L H X HLLHLLHH LLLHLLLH L L H H L L L H L H H H L L L H L H H H L L H H H H L H L L H L H L H H H L H X H L H H H L H X H L L H L L H H L L L H L L L H L L H H L L L H L H H H L L L H...

Page 272: ...LE IS TOO LONG IF YOURS DOES DELETE THIS DESCRIPTION FROM HERE TO END OF FILE This PAL implements the main state machine of the DRAM controller The state machine is described below For brevity the fol...

Page 273: ...mpled A21 I MUXOE MUXOE maintain MUXOE state I 1 I lalways v 1 I state ACCESS4 0111 fourth cycle of access or refresh I I IRASO IA2REG MUXOE RAS corresponding to A2 I I IRASI A2REG MUXOE or refresh I...

Page 274: ...N ON lAM AM lAM AM AM A2REG MUXOE 111 IAI AI AS A2 STARTACCESS 10 I lAM AM lAS AS OFFOFF AI A2 STARTACCESS i nterl eave ROWSEL QO Ql CLK 00 01 11 10 ROWSEL state circled 00 I OWI0 0111 key ROWSEL Ql Q...

Page 275: ...RAM State PAL are guaranteed even with a large CLK2 to CLK skew because the Refresh Interval Counter PAL is clocked by the rising edge of CLK and the RFRQ output is only sampled by the DRAM State PAL...

Page 276: ...hase DISABLE DRAM STATE PAL Disable controls during Middle Of Phase MUXOE refresh PAL OUTPUTS Name Connects To PAL Usage Changes State CASO DRAM Byte 0 Start Of Phase for CAS1 DRAM Byte 1 Controls DRA...

Page 277: ...ClK DT R DISA8lE ROWSEl WC ROY ClK 8EI ROWSEl CASI CAS2 ROWSEl ClK DT R DISA8lE ROWSEl WC ROY ClK BE2 ROWSEl CAS2 CAS3 ROWSEl ClK DT R DISABlE ROWSEl WC ROY ClK 8E3 ROWSEl CAS3 drop CAS on read drop o...

Page 278: ...H X X X X X H L L C L X X X X X H L DESCRI PTION XXXXXHXL H H H H L H H L HHHHHHHL H H H H L H H L LLLLLLHH LLLLLLHH LLLLLLLH LLLLLLLL HHHHLHLL HHHHHHHL HHHHHLHH H L L H H L H H HLLHHLLH HLLHHLLL HHHH...

Page 279: ...T R DEN ROWSEL DEN BEI DISABLE CAS2 ROWSEL DT R CLK DISABLE ROWSEL DT R DEN ROWSEL DEN BE2 DISABLE CAS3 ROWSEL DT R CLK DISABLE ROWSEL DT R DEN ROWSEL DEN BE3 DISABLE drop CAS on read maintain CAS on...

Page 280: ...X X X X X H L LCLXXXXXHL DESCRIPTION xX X X X H X H initialize to IDLE H H H H L H H H IDLE DT R tracking W R H H H H H H H H IDLE DT R tracking W R H H H H L H H H IDLE DT R tracking W R L L L L L L...

Page 281: ...me Connects From PAL Usage Sampled REFACKO DRAM RASO Indicates when refresh Every ClK that REFACK1 DRAM RAS1 starts turns off RFRQ RFRQ is active NCO NC1 NC2 NC3 Not connected Not used Never NC4 NC5 N...

Page 282: ...Q3 Q7 Q6 Q5 Q4 Q3 QO Q2 Q7 Q6 Q5 Q4 Q3 Q7 Q6 Q5 Q4 Q3 QI QO Q3 Q7 Q6 Q5 Q4 Q3 Q7 Q6 Q5 Q4 Q3 Q2 QI QO Q4 Q7 Q6 Q5 Q4 Q3 Q7 Q6 Q5 Q4 Q3 Q3 Q2 QI QO Q5 Q7 Q6 Q5 Q4 Q3 Q7 Q6 Q5 Q4 Q3 Q4 Q3 Q2 Ql QO Q6 Q...

Page 283: ...H L inputs outputs COMMENTS initial ize ignore errors decrement decrement decrement decrement to 7 reset to 255 decrement activate RFRQ decrement sample REFACKs decrement sample REFACKs on vector decr...

Page 284: ...MUXOE outputs enable on refresh PAL INPUTS Name Connects From PAL Usage Sampled NCO NC1 NC2 NC3 Not connected Not used Never NC4 NC5 NC6 NC7 PAL OUTPUTS Name Connects To PAL Usage Changes State 00 Mux...

Page 285: ...A4 A5 A6 A7 VCC AO AO least significant bit of 8 bit counter AI Al AO AI AO A2 A2 Al AO A2 AI A2 AO A3 A3 A2 Al AO A3 A2 A3 AI A3 AO A4 A4 A3 A2 Al AO A4 A3 A4 A2 A4 AI A4 AO A5 A5 A4 A3 A2 Al AO A5...

Page 286: ...alize ignore any errors on this vector L C L L L L L L L L increment L C L L L L L L L H increment L C L L L L L L H L increment L C L L L L L L H H increment L C L L L L L H L L increment H H Z Z Z Z...

Page 287: ...TIONS TIMING PARAMETERS Figure C 8 shows the timing of signals for DRAM read and write cycles Table C 5 displays the worst case timing parameters for six DRAM circuits each of which uses a different t...

Page 288: ...s R l c I e r t Iep CSH tCRp l ICRP R l tCSH IR I CASt _________ I H twCS tcw tWCH tWRP l r 1RWH IRWL Iw I i w WEI 1 I tl IMUX tASR I AH I CAR I f 1ASR t tRAH t tASC1 tC H IAsl tCAH ct _ t MUX j 1 1 1...

Page 289: ...r 386 12 o wri te data out delay ClK2 I 386 Date 50 50 50 50 50 50 0 I ClK2 I 386 Data m l J 386 t21 o read data llet l4l 386 Datll ClK2 I 0 10 10 0 10 10 10 10 CII J 386 22 o read data hold ClK2 I 3...

Page 290: ...9999 25 9999 2S 9999 0 CAS DrarMddr DRAM tAR I eolum addr hold fr RASII RAS Dr8IMddr 40 9999 40 9999 60 0999 70 9999 90 9999 80 9999 Z RAS DramAddr rJ DRAM tON output buffer turn 00 CAS rd data 20 99...

Page 291: ...0 148 180 174 204 180 198 228 264 0 I HwrtIJAIT t1 1 1 1 Q m I AS CAS 174 204 174 204 228 264 174 204 180 198 228 264 CJ CAS pulse width rd eyel 35 9999 0 DRAM CAS 15 9999 20 9999 25 9999 30 9999 85 9...

Page 292: ...39 n 57 92 39 n 43 70 57 92 tI DRAM tCAH colum address hold 10 9999 10 9999 15 9999 20 9999 25 9999 25 9999 I I tHUX p t1 t1 R J CAS DramAddr 85 119 85 119 112 149 85 119 87 115 112 149 CJJ 0 tNUX p...

Page 293: ...E 114 146 114 146 230 270 176 210 178 206 230 270 r 0 C I m DRAM tRRH read COlD hold ref to RAS 109999 10 9999 109999 109999 20 9999 10 9999 en W 1 1 tBAK28AK Q HAst WE 114 146 114 146 230 270 176 210...

Page 294: ...C256 15 data in set up time 09999 09999 09999 09999 112 UCVR wrt daU CAS 5 73 12 75 23 93 5 73 data in hold time 20 9999 20 9999 20 9999 25 9999 twrU AIT t1 R CAS DrllillOata 115 185 113 178 151 225 1...

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