121
Memory Controller
7.7
DDR Termination Voltage
The
V
TT
DDR termination voltage must track the
V
DDQ
and provide the termination voltage to the
termination resistors. This tracking must be 50 percent of (
V
DDQ
-
V
SSQ
) over voltage,
temperature, and noise. It must maintain less than 40 mV offset from
V
REF
over these conditions.
This voltage must be low-impedance and source-significant current. The source and sink DC
current for signal termination is at its absolute maximum current of 2.6 A-2.9 A for a 64/72-bit
DIMM.
7.8
DDR V
REF
Voltage
The
shows the DDR Vref voltage. The DDR
V
REF
is a low-current source (supplying
input leakage and small transients). It must track 50 percent of (
V
DDQ
-
V
SSQ
) over voltage,
temperature, and noise. Use a single source for
V
REF
to eliminate variation and tracking of
multiple generators. Maintain 15-20 mils clearance around other nets. Use a distributed decoupling
scheme. Use a simple resistor divider with 1% or better accuracy.
Note:
The 100 ohm resistors can be replaced with 1K +/- 1% resistors to minimize leakage current during
battery backup mode.
Figure 61.
DDR V
REF
Circuit
100 ohms
2.5/1.8V
100 ohms
0.1uF
DDR VREF
0.1uF
0.1uF
Summary of Contents for 80331
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