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12

Specification Update

Intel

®

80219 General Purpose PCI Processor

Identification Information

Die Details

Stepping

Part Number

QDF (Q)/

Specification Number (SL)

Voltage (V)

Intel

®

80219 General

Purpose PCI Processor

Speed (MHz)

Notes

A-0

A-0

A-0

A-0

FW80219M400

FW80219M600

FW80219M400

FW80219M600

Q690

Q691

SL7CL

SL7CM

3.3

3.3

3.3

3.3

400

600

400

600

Samples

Samples

Production Material

Production Material

Device ID Registers

Device and Stepping

Processor Device ID

(CP15, Register0 - opcode_2=0)

ATU Device ID

(ATUDID)

ATU Revision ID

(ATURID)

JTAG Device ID

A-0 (400 MHz)

A-0 (600 MHz)

0x69052E20

0x69052E30

0x031A

0x031B

0x00

0x00

0x0927E013

0x0927F013

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Summary of Contents for 80219

Page 1: ...ice The Intel 80219 General Purpose PCI Processor 80219 may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized e...

Page 2: ...Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of docu...

Page 3: ...eral Purpose PCI Processor Contents Revision History 5 Preface 6 Summary Table of Changes 7 Identification Information 11 Core Errata 13 Non Core Errata 20 Specification Changes 24 Specification Clari...

Page 4: ...4 Specification Update Intel 80219 General Purpose PCI Processor This Page Left Intentionally Blank...

Page 5: ...ification Update 5 Intel 80219 General Purpose PCI Processor Revision History Revision History Date Version Description July 2004 002 Added Specification Clarification 7 November 2003 001 Initial Rele...

Page 6: ...shed specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specificat...

Page 7: ...es the following notations Codes Used in Summary Table Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This...

Page 8: ...rupt Protected Registers 7 X 15 NoFix Load Immediately Following a DMM Flush Entry is Also Flushed 8 X 15 NoFix Trace Buffer Does Not Operate Below 1 3 V 9 X 15 NoFix Data Cache Unit Can Stall for a S...

Page 9: ...I Mode 3 X 21 NoFix MCU Pointers are Incorrect following a Restoration from a Power Fail 4 X 21 NoFix PMU Does Not Account for when the Arbiter Deasserts GNT One Cycle before FRAME 5 X 21 NoFix Lost D...

Page 10: ...al Bus Specification Revision 2 3 2 X 26 NoFix Modifications to the Hot Debug procedure are necessary for the Intel 80219 general purpose PCI processor when flat memory mapping is not used Virtual Add...

Page 11: ...date 11 Intel 80219 General Purpose PCI Processor Identification Information Identification Information Markings Figure 1 Topside Markings Intel 80219 General Purpose PCI Processor SLxxx M 2001 FPO FW...

Page 12: ...Notes A 0 A 0 A 0 A 0 FW80219M400 FW80219M600 FW80219M400 FW80219M600 Q690 Q691 SL7CL SL7CM 3 3 3 3 3 3 3 3 400 600 400 600 Samples Samples Production Material Production Material Device ID Registers...

Page 13: ...1 description of the SAMPLE PRELOAD instruction states that When the SAMPLE PRELOAD instruction is selected the state of all signals flowing through system pins input or output shall be loaded into t...

Page 14: ...clock may read the bit before it updates in the register thus reading the old value Workaround The JTAG clock should be slower than the core clock Status NoFix 5 Extra Circuitry Is Not JTAG Boundary S...

Page 15: ...n the case of STC only Rn is corrupted Unexpected memory accesses can also occur In the case of an LDC any memory location may be accessed since the FIQ registers may be improperly used as the base re...

Page 16: ...into the cache at address A 2 another master externally modifies address A 3 a core store instruction attempts to modify A hits the cache aborts because of MMU permissions and is backed out of the cac...

Page 17: ...so be monitored using performance monitoring event 0x6 during the same time period as event 0x1 The mispredicted branch number can then be subtracted from the instruction cache stall number generated...

Page 18: ...Instead an unpredictable value is returned Workaround No workaround Status NoFix 14 Disabling and re enabling the MMU can hang the core or cause it to execute the wrong code Problem When the MMU is d...

Page 19: ...parallel JTAG registers incorrectly require an extra TCK rising edge to make the update visible Therefore operations like hold reset JTAG break and vector traps require either an extra TCK cycle by go...

Page 20: ...enough data to get to the next QWORD boundary It does not do this Instead it returns invalid data in the high DWORD of the second QWORD data from a previous fetch and the transaction is corrupted This...

Page 21: ...biter deasserts GNT in PCI X mode the requestor can still start a transaction for one cycle due to allowed pipelining In this situation the PMU does not properly detect the FRAME as the ATU and contin...

Page 22: ...or more information on the MTTR1 function Implication In the case of the MCU internal bus target this problem is compounded by the many internal bus retries that are issued by the MCU when under heavi...

Page 23: ...rature manufacturing testing 80219 silicon is subjected to a 0 C environment for an extended period of time During this time the Vih test is implemented and the junction temperature is at or near the...

Page 24: ...control the IDSEL to the I O device External circuitry is no longer required other than a simple switch The output function of the P_BMI signal is controlled by the GPIO Output Data Register GPOD Bit...

Page 25: ...r I O device configuration and resource falls to the 80219 firmware Figure 2 Intel 80219 General Purpose PCI Processor P_BMI Signal Implementation for Intel 80219 General Purpose PCI Processor B 0 B 1...

Page 26: ...Hot Debug procedure are necessary for the Intel 80219 general purpose PCI processor when flat memory mapping is not used Virtual Address Physical Address Issue The Intel 80219 general purpose PCI proc...

Page 27: ...ically during boot up to determine the total amount o SDRAM installed Instead either use the Serial Presence Detect SPD mechanism or have it hard coded in firmware SPD is used to read via I2C from a n...

Page 28: ...might fetch the remaining 92 byes from 0x4000 0x405C Both buffers have the ability to access the internal bus without preference i e either buffer may gain access first Therefore it is possible the 9...

Page 29: ...Specification Update 29 Intel 80219 General Purpose PCI Processor Documentation Changes Documentation Changes None for this revision of this specification update...

Page 30: ...30 Specification Update Intel 80219 General Purpose PCI Processor Documentation Changes This Page Left Intentionally Blank...

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