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CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Advanced Chipset Features
> DRAM Timing Settings Press Enter
> AGP Function Settings Press Enter
In-Order Queue 4-Level
Concurrent PCI/Host Enabled
I/O Recovery Time Disabled
CPU to PCI Post Write Enabled
CPU to PCI Dynamic Burst Disabled
PCI Delay Transaction Disabled
Memory Parity/ECC Check Disabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
Memory Hole Disabled
Item Help
Menu Level >
↑↓→←
↑↓→←
↑↓→←
↑↓→←
Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
DRAM Timing Settings
Please refer to section 3-6-1
AGP Function Settings
Please refer to section 3-6-2
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Parity/ECC Check
This function provides parity check of memory.
The choice is either Disabled or Enabled.
3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
DRAM Timing Settings
