Intel 6300ESB ICH, Design Manual

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January 2007 55
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
4.1.4 Length Matching Constraints
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routing
lengths for each signal group, which are recommended to achieve optimal SI and timing. In
addition to the absolute length limits provided in the individual guideline tables, there are more
restrictive length matching requirements called length-matching constraints. These additional
requirements further restrict the minimum to maximum length range of each signal group with
respect to clock strobe, within the overall boundaries defined in the guideline tables, as required to
ensure adequate timing margins.
The amount of minimum to maximum length variance allowed for each group around the clock
strobe reference length varies from signal group to signal group depending on the amount of timing
variation that may be tolerated. Refer to
Table 6 for source synchronous data matching
requirements and Table 7 for source synchronous address matching requirements.
Address
Group 2
A31# 773 HA31# 617
A30# 773 HA30# 484
A29# 773 HA29# 558
A28# 773 HA28# 579
A27# 773 HA27# 631
A26# 773 HA26# 556
A25# 773 HA25# 535
A24# 773 HA24# 353
A23# 773 HA23# 382
A22# 773 HA22# 545
A21# 773 HA21# 429
A20# 773 HA20# 414
A19# 773 HA19# 284
A18# 773 HA18# 389
A17# 773 HA17# 457
ADSTB[1]# 773 HADSTB[1]# 504
Host Clocks
BCLK0 447 BCLK 1138
BCLK1 447 BCLK# 1145
ITP Signals BPM[3:0] 593 — —
Table 9. Intel
®
Pentium
®
M/Celeron
®
M Processor and GMCH Source Synchronous
FSB Signal Package Lengths (Sheet 6 of 6)
Signal
Group CPU Signal
Name
Intel
®
Pentium
®
M/Celeron
®
M
Processor Package
Trace Length (mils)
GMCH Signal
Name
GMCH Package Trace
Length (mils)