Intel 6300ESB ICH, Design Manual

Page: 243 / 320

January 2007 243
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
16 Core Output 3.3 V
May leave as no
connect
17 Core Output 3.3 V
18 Core Output 5 V
19 Core Output 5 V
20 Core Output 5 V
21 Core Output 5 V
23 Core Output 5 V
24 Resume Input-Output
†
3.3 V
25 Resume Input-Output
†
3.3 V
27 Resume Input-Output
†
3.3 V
28 Resume Input-Output
†
3.3 V
32 Core Input-Output
†
3.3 V
33 Core Input-Output
†
3.3 V
34 Core Input-Output
†
3.3 V
35 Core Input-Output
†
3.3 V
36 Core Input-Output
†
3.3 V
37 Core Input-Output
†
3.3 V
May leave as no
connect
38 Core Input-Output
†
3.3 V
39 Core Input-Output
†
3.3 V
40 Core Input-Output
†
3.3 V
41 Core Input-Output
†
3.3 V
42 Core Input-Output
†
3.3 V
43 Core Input-Output
†
3.3 V
56 RTC Output 3.3 V
57 RTC Output 3.3 V
† Defaults as an Output to the 6300ESB.
Table 102. GPIO Summary (Sheet 2 of 2)
GPIO Number Power Well Input-Output Tolerance If Not Used