Intel 6300ESB ICH, Design Manual

Page: 211 / 320

January 2007 211
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.6.1.2 USB 2.0 Trace Separation
Use the following separation guidelines. Figure 108 provides illustration of the recommended trace
spacing.
1. Maintain parallelism between USB differential signals with the trace spacing needed to
achieve the target differential impedance. Deviations will normally occur due to package
breakout and routing to connector pins. Just ensure the amount and length of the deviations are
kept to the minimum possible.
2. Use an impedance calculator to determine the trace width and spacing required for the specific
board stackup being used; keeping in mind the target differential impedance.
3. Minimize the length of high-speed clock and periodic signal traces that run parallel to
High-speed USB signal lines, to minimize crosstalk. Based on EMI testing experience, the
minimum suggested spacing to clock signals is 100 mils.
4. Based on simulation data, use 45 mils minimum spacing between high-speed USB signal pairs
and other signal traces for optimal signal quality. This helps to prevent crosstalk.
9.6.1.3 USB BIAS Connections
The USBRBIAS pin and the USBRBIAS# pin may be shorted and routed 5 mils width, 5 mils
spacing, to one end of a 22.6
Ω
±
1% resistor to ground. Place the resistor within 500 mils of the
6300ESB and avoid routing next to clock pins. (See Figure 109 and Table 82 for more
information.)
Figure 107. Trace Routing
B1159-01
45”
Figure 108. Recommended General USB Trace Spacing (55
Ω
± 10%)