Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.6 USB 2.0
9.6.1 Layout Guidelines
Note: These routing guidelines are created using the stack-ups described in Section 3.1, “Nominal Board
Stack-Up” on page 33 .
9.6.1.1 General Routing and Placement
Use the following general routing and placement guidelines when laying out a new design. These
guidelines will help to minimize signal quality and EMI problems.
1. Place the 6300ESB and major components on the un-routed board first. With minimum trace
lengths, route high-speed clock, periodic signals, and USB 2.0 differential pairs first. Maintain
maximum possible distance between high-speed clocks/periodic signals to USB 2.0
differential pairs and any connector leaving the PCB (i.e., I/O connectors, control and signal
headers, or power connectors).
2. USB 2.0 signals should be ground referenced (on recommended stackup this would be bottom
signal layer).
3. Route USB 2.0 signals using a minimum of vias and corners. This reduces reflections and
impedance changes.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single
90° turn. This reduces reflections on the signal by minimizing impedance discontinuities. (See
Figure 107 .)
5. Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers, magnetic devices
or ICs that use and/or duplicate clocks.
6. Stubs on High-speed USB signals should be avoided, as stubs will cause signal reflections and
affect signal quality. When a stub is unavoidable in the design, the total of all the stubs on a
particular line should not be greater than 200 mils.
7. Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing
over anti-etch when possible. Crossing over anti-etch (plane splits) increases inductance and
radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0
traces as much as practical. It is preferable to change layers to avoid crossing a plane split.
Refer to
Section 9.6.2, “Plane Splits, Voids and Cut-Outs (Anti-Etch)” on page 213 .
8. Separate signal traces into similar categories and route similar signal traces together (such as
routing differential pairs together).
9. Keep the USB 2.0 signals clear of the core logic set. High current transients are produced
during internal state transitions and may be very difficult to filter out.
10. Follow the 20 x h thumb rule by keeping traces at least 20 x (height above the plane) away
from the edge of the plane (VCC or GND, depending on the plane the trace is over). For the
suggested stackup the height above the plane is 4.5 mils. This calculates to a 90 mils spacing
requirement from the edge of the plane. This helps prevent the coupling of the signal onto
adjacent wires and also helps prevent free radiation of the signal from the edge of the PCB.