January 2007
203
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
Note:
AC_BIT_CLK, SDATA_OUT, SDATA_IN, SYNC all need to be routed on the same layer and NO
layer changes are allowed.
9.4.1
AC’97 Routing
To ensure the maximum performance of the codec, proper component placement and routing
techniques are required. These techniques include properly isolating the codec, associated audio
circuitry, analog power supplies, and analog ground planes, from the rest of the motherboard. This
includes plane splits and proper routing of signals not associated with the audio section. Contact
your vendor for device-specific recommendations.
The basic recommendations are as follows:
•
Special consideration must be given for the ground return paths for the analog signals.
•
Digital signals routed in the vicinity of the analog audio signals must not cross the power plane
split lines. Analog and digital signals should be located as far as possible from each other.
•
Partition the board with all analog components grouped together in one area and all digital
components in another.
•
Separate analog and digital ground planes must be provided, with the digital components over
the digital ground plane, and the analog components, including the analog power regulators,
over the analog ground plane. The split between planes must be a minimum of 0.05 inches
wide.
•
Keep digital signal traces, especially the clock, as far as possible from the analog input and
voltage reference pins.
•
Do not completely isolate the analog/audio ground plane from the rest of the board ground
plane. There should be a single point (0.25 inches to 0.5 inches wide) where the
analog/isolated ground plane connects to the main ground plane.
•
Any signals entering or leaving the analog area must cross the ground split in the area where
the analog ground is attached to the main motherboard ground. That is, no signal should cross
the split/gap between the ground planes, which would cause a ground loop, thereby greatly
increasing EMI emissions and degrading the analog and digital signal quality.
•
Analog power and signal traces should be routed over the analog ground plane.
•
Digital power and signal traces should be routed over the digital ground plane.
•
Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the
shortest connections to pins, with wide traces to reduce impedance.
Table 78.
AC’97 AC_SDIN Routing Summary
Trace
Impedance
AC’97 Routing
Requirements
Trace Lengths
Series Termination
Resistance
AC_SDIN Signal
Length Matching
55
Ω
± 10%%
5 mil width, 10 mil
spacing (based on
stackup assumptions
in
Y1 = 3 to 6 inches
Y2 = 3 to 8 inches
Y3 = 0.1 to 0.5 inches
Y4 = 0.1 to 0.5 inches
Y5 = 3 to12 inches
R1 = 34
Ω
- 38
Ω
R2 =R1
N/A
Summary of Contents for 6300ESB ICH
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Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
