Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.2 IDE Interface
Note: These routing guidelines are created using the stack-up described in Section 3.1, “Nominal Board
Stack-Up” on page 33 .
This section contains guidelines for connecting and routing the 6300ESB IDE interface. The
6300ESB has two independent IDE channels. This section provides guidelines for IDE connector
cabling and motherboard design, including component and resistor placement, and signal
termination for both IDE channels. The 6300ESB has integrated the series resistors that have been
typically required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA
connectors. While it is not anticipated that additional series termination resistors will be required,
OEMs should verify motherboard signal integrity through simulation. Additional external 0
Ω
resistors may be incorporated into the design to address possible noise issues on the motherboard.
The additional resistor layout increases flexibility by offering stuffing options at a later date. When
used, place these resistors close to the connector.
The IDE interface must be routed with 5 mil width traces, 7 mil spacing (dependent upon stackup
parameters), and must be less than eight inches long (from 6300ESB to IDE connector). See
Table 75 below for routing summary.
Note: A max of two layer transitions are allowed. All transitions must be routed within 1.5 inches from
the 6300ESB pin. After the 1.5 inch layer transition boundary, all strobe and data signals must be
routed on the same layer. No layer transitions are allowed at the IDE connector.
9.2.1 Cabling
Length of cable: Each IDE cable must be equal to 18 inches.
Capacitance: Less than 35 pF.
Placement: A maximum of six inches between drive connectors on the cable. When a single drive
is placed on the cable, it should be placed at the end of the cable. When a second drive is placed on
the same cable, it should be placed on the next closest connector to the end of the cable (six inches
away from the end of the cable).
Table 74. IDE Signal Groups
Signal Group Primary Secondary
Data PDD[15:0] SDD[15:0]
Strobes PDIOR# (write)
PDIORDY (read)
SDIOR# (write)
SDIORDY (read)
Table 75. IDE Routing Summary
Trace
Impedance
IDE Routing Requirements
Maximum
Trace Length
IDE Signal Length Matching
55
Ω
± 10%
5 mil width, 7 mil spacing
(based on stackup
assumptions in
Section 3.1 )
8 inches
The two strobe signals must be matched
within 100 mils of each other.
The data lines must be within ± 500 mils of
the average length of the two strobe
signals.