Intel 6300ESB ICH, Design Manual

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162
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
6.3.1 DVO Interface Signal Groups
Table 48 shows the DVO interface signal groups.
6.3.1.1 DVO/I
2
C to AGP Pin Mapping
The DVODETECT signal is muxed with the GPAR signal on the AGP bus. This signal will act as a
strap to indicate if the interface is in AGP or DVO mode. The GMCH has an internal 8.2-k,
pull-down on this signal that will naturally pull it low. If an AGP graphics device is present, the
signal will be pulled high at the AGP graphics device and the AGP/DVO mux select bit in the
SHIC register will be set to AGP mode.
The SBA[7:0] signals act as straps for an ADDID. These pins are used to communicate to the
Video BIOS when an external device is interfaced to the DVO port. If an on-board DVO device is
implemented, ADDID[7] should be strapped low. When an AGP graphics device is present,
DVODETECT=1 (AGP mode).
Table 48. DVO Interface Signal Groups
Signal
Group GMCH Signal
Name
Signal
Type
Signal
Group GMCH Signal
Name
Signal
Type
DVOB
DVOBFLDSTL Input
DVOC
DVOCFLDSTL Input
DVOBHSYNC Output DVOCHSYNC Output
DVOBVSYNC Output DVOCVSYNC Output
DVOBBLANK# Output DVOCBLANK# Output
DVOBD[11:0] Output DVOCD[11:0] Output
DVOBCLK
(DVOBCLK[0])
Output
Strobe
DVOCCLK
(DVOCCLK[0])
Output
Strobe
DVOBCLK#
(DVOBCLK[1])
Output
Strobe
DVOCCLK#
(DVOCCLK[1])
Output
Strobe
Common
Signals for
Both DVO
Ports
DVOBCCLKINT Input
Voltage
Reference,
RCOMP
DVORCOMP
DVOBCINTR# Input
ADDID[7:0] Input
GVREF
DVODETECT Input