Intel 6300ESB ICH, Design Manual

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108
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.8.1 Intel 855GME Chipset and Decoupling Guidelines
Decoupling in Table 24 is based on the voltage regulator solution used on the customer reference
board design.
4.8.1.1 GMCH VCCSM Decoupling
For the VCCSM pins of the GMCH, a minimum of eleven 0603 form factor, 0.1 µF, high-
frequency capacitors is required and must be placed within 150 mils of the GMCH package. The
capacitors shall be evenly distributed along the GMCH DDR system memory interface and placed
perpendicular to the GMCH with the power (2.5 V) side of the capacitors facing the GMCH.
•
Every GMCH ground and VCCSM power ball in the system memory interface shall have its
own via.
•
Each capacitor shall also have its own 2.5 V via within 25 mils of the capacitor pad for
connecting to a 2.5 V copper flood. The traces from the capacitors shall also be wide and
connect to the outer row of balls on the GMCH.
•
The ground end of each capacitor must connect to the ground flood and to the ground plane
through a via. Each via shall be as close to the associated capacitor pad as possible, within
25 mils and with as thick a trace as possible.
•
The system memory interface also requires low frequency decoupling. Place two 150 µF
electrolytic capacitors between the GMCH and the first DIMM connector.
Table 24. GMCH Decoupling Recommendations
Pin Name Configuration F Qty TYPE Notes
VCC
Connect to
VCC1_35S
0.1 µF
10 µF
150 µF
4
1
2
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SPC, E, 6.3 V, 20%
1 X 0.1 µF within 200 mils
3 X 0.1 µF on bottom side
VTTLF Connect to VCCP
0.1 µF
10 µF
150 µF
2
1
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SPC, E, 6.3 V, 20%
2 X 0.1 µF on bottom side
VTTHF
Connect to caps
directly
0.1 µF 5 XR7, 0603, 16 V, 10%
VCCHL
Connect to
VCC1_35S
0.1 µF
10 µF
2
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
1 X 0.1 µF within 200 mils
1 X 0.1 µF on bottom side
VCCSM
Connect to
VCCSus2_5
0.1 µF
150 µF
11
2
XR7, 0603, 16 V, 10%
TANT, D, 10 V, 20%
Refer to Section 4.8.1.1
for more information.
VCCDVO
Connect to
VCC1_5S
0.1 µF
10 µF
150 µF
2
1
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SPC, E, 6.3 V, 20%
1 X 0.1 µF within 200 mils
1 X 0.1 µF on bottom side
VCCDLVDS
Connect to
VCC1_5S
0.1 µF
22 µF
47 µF
1
1
1
XR7, 0603, 16 V, 10%
TANT, B, 10 V, 20%
TANT, D, 10 V, 20%
1 X 0.1 µF within 200 mils
VCCTXLVDS
Connect to
VCCSus2_5
0.1 µF
22 µF
47 µF
3
1
1
XR7, 0603, 16 V, 10%
TANT, B, 10 V, 20%
TANT, D, 10 V, 20%
1 X 0.1 µF within 200 mils
2 X 0.1 µF on bottom side
VCCGPIO
Connect to
Vcc3_3S
0.1 µF
10 µF
1
1
XR7, 0603, 16 V, 10%
XR5, 1206, 6.3 V, 20%
SMVREF 0.1 µF 1 XR7, 0603, 16 V, 10% 1 X 0.1 µF on bottom side