1000BASE-T/100BASE-TX/10BASE-T Physical Layer Compliance Tests Manual
Intel Confidential
147
100Base-TX Test Procedure for the 82544 Chip
Figure I-12. Fall-Time, 90% Cursor (left) and 10% Cursor (right)
Note:
Note: In many plots, the cursors almost never end up exactly on the 10% and 90% voltage levels.
This is because even with the vertical scale set to provide best-case vertical resolution, the smallest
discrete vertical increment is 3 mV. Consequently, one should try to position both cursors to the
closest adjacent points on the slope nearest to the 10% and 90% voltage points.
For the sake of brevity (and to avoid repetition) example plots are NOT provided for a negative
pulse.
Repeat all of these steps for both a positive pulse and for a negative pulse.
I.4.8
9.1.6 Rise and Fall Times
Measured Rise and Fall times shall be between 3.0 and 5.0 nsec.
Rise to Fall delta shall be < 0.5 nsec.
Measured rise and fall times must be within the range between 3.0 nsec. and 5.0 nsec.
The maximum variation in any rise time with respect to any fall time shall be 0.5 nsec or less.
Table A-2. 9.1.6 Rise and Fall Times
UUT
Time (nsec.)
Positive Rise Time ns.
4.88
Positive Fall Time ns.
4.84
delta Pos. rise/fall time
0.04 nsec.
Negative Rise Time ns.
4.72
Negative Fall Time ns.
4.88
delta Neg. rise/fall time
0.16 nsec
Pass/Fail
PASS