DTR-4.6
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS
IC42S16100 (16-Mbit Synchronous Dynamic RAM)
BLOCK DIAGRAM
PIN LAYOUT
1
CLK
CKE
CS
RAS
CAS
WE
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
ROW
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
ROW DECODER
ROW DECODER
11
11
11
11
8
11
11
MEMORY CELL
ARRAY
BANK 0
COLUMN DECODER
MEMORY CELL
ARRAY
BANK 1
SENSE AMP I/O GATE
SENSE AMP I/O GATE
2048
2048
8
256
256
DATA IN
BUFFER
DATA OUT
BUFFER
DQM
I/O 0-15
Vcc/VccQ
GND/GNDQ
16
16
16
16
1
2
3
4
5
6
7
8
22
23
24
25
50
49
48
47
46
45
44
43
29
28
27
26
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
A1
A2
A3
VCC
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
VCCQ
UDQM
A6
A5
A4
GND
Pin No.
Pin name
Function
20 to 24
27 to 32
A0-A10
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input
and A0-A7 as column address inputs during read or write command input. A10 is also used to
determine the precharge mode during other commands. If A10 is LOW during precharge command,
the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically after
the burst access.
These signals become part of the OP CODE during mode register set command input.
19
A11
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is
selected. This signal becomes part of the OP CODE during mode register set command input.
16
CAS
CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth
Table" item for details on device commands.
34
CKE
The CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode,
or the self refresh mode. The CKE is an asynchronous input.
35
CLK
CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired
in synchronization with the rising edge of this pin.
18
CS
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in
the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
I/O0
to
I/O15
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and
UDQM pins.
14, 36
LDQM,
UDQM
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and
UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to theHIGH
impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to
the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device.
17
RAS
RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth
Table" item for details on device commands.
15
WE
WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth
Table" item for details on device commands.
7, 13, 38, 44
V
CC
Q
V
CC
Q is the output buffer power supply.
1, 25
V
CC
V
CC
is the device internal power supply.
4, 10, 41, 47
GNDQ
GNDQ is the output buffer ground.
26, 50
GND
GND is the device internal ground.
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