![Infineon XDPP1100 Technical Reference Manual Download Page 83](http://html1.mh-extra.com/html/infineon/xdpp1100/xdpp1100_technical-reference-manual_2055193083.webp)
User Manual
83 of 562
V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Voltage control
Care should be taken if using this feature during active regulation, because the power stage may not be capable
of tracking large steps in the target voltage without significant overshoot/undershoot.
The ramp generator also provides the following read-only status registers:
•
vc_vcontrol_at_target
indicates vcontrol_ramp is at the target voltage and is no longer slewing
•
vc_vcontrol_ramp_busy
indicates vcontrol_ramp is slewing to a new target
•
vc_vcontrol_ramp_rise
and
vc_vcontrol_ramp_fall
indicate the direction of the vcontrol_ramp change
5.3
Interrupts
The voltage control interrupt generation is illustrated in
. The interrupts are generated based on the
following ramp generator outputs:
•
vc_vcontrol_at_target
, which is the previously discussed read-only register
•
vc_vcontrol_at_target_window
, which is an internal signal that indicates vcontrol_ramp is within a
window around the target voltage
The target voltage window is defined by parameter
vc_vramp_target_window
, and this indicator may be used
to change system behavior prior to arriving at the target voltage, such as turning on the SR FETs during the
diode emulation soft-start.
Figure 41
Interrupts diagram
An interrupt is enabled by setting the appropriate bit high in the register
vc_vcontrol_irq_en
, and
correspondingly interrupts are cleared by setting the same bit low in the register
vc_vctonrol_irq_en
. The
interrupt status is observable via read-only register
vc_vcontrol_irq_status
.
5.4
Multi-segment droop (load-line)
The XDP1100 multi-segment droop module allows programming of three independent droop resistances at
positive current as well as an independent negative current droop resistance, as shown in
vc_vcontrol_irq_en[1]
vc_vcontrol_at_target_window
vc_vcontrol_irq_en[0]
vc_vcontrol_at_target
vc_vcontrol_irq
vc_vcontrol_irq_stat[1]
vc_vcontrol_irq_stat[0]
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR