User Manual 485 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
0: No change to DMA error interrupt
1: Clear DMA error interrupt
ISR
DMA_CH_INT_SET
W
5000_1010h [15:0]
DMA channel interrupts set.
For each bit [x]:
0: No change to DMA channel x
interrupt
1: Set DMA channel x interrupt
ISR
DMA_ERR_INT_SET W
5000_1010h [31]
DMA error interrupt set.
0: No change to DMA error interrupt
1: Set DMA error interrupt
15.7
General-purpose input output (GPIO) module
The CPUS provides a number of GPIO pins, which are organized into blocks of eight GPIO pins each. The
XDPP1100 controller contains two GPIO blocks (identical instance, replicated twice): GPIO0 and GPIO1.
Each GPIO register set can be accessed with a different base address:
•
GPIO_0: 6004_0000h
•
GPIO_1: 6005_0000h
GPIO pin mapping on primary XDPP1100 IOs is summarized in
The GPIO block is an Arm® PrimeCell IP (PL061); extensive documentation can be found in the
“A
rm® PrimeCell
General Purpose
Input/Output (PL061) Technical Reference Manual”.
The main features of the GPIO block are:
•
Eight individually programmable input/output pins, default to input at reset
•
HW control capability of GPIO lines for different system configurations
•
Bit masking in both read and write operations through address lines
•
Programmable interrupt generation capability, from a transition or a level condition, on any number of pins
15.7.1
GPIO registers
The relevant GPIO-related registers and their descriptions are provided in
Table 106
GPIO register description
Register name Field name
Access Address
Bits
Description
GPIODATA
DATA
RW
6004_0000h
6005_0000h
[7:0]
The GPIODATA register is the data
register. In software control mode,
values written in the GPIODATA
register are transferred onto the
GPOUT pins if the respective pins
have been configured as outputs
through the GPIODIR register.
