User Manual 477 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
15.6.1
DMA block diagram
The DMA block diagram is shown in
Figure 112
DMA block diagram
The APB block contains the registers that enable the configuration of the controller by using the APB slave
interface.
The controller AHB block contains a single AHB-Lite master that enables it to transfer data from a source AHB
slave to a destination AHB slave using a 32-bit data bus. The controller is compliant with the AMBA® 3 AHB-Lite
protocol. For detailed information about the AHB-Lite interface, see the AMBA® 3 AHB-Lite Protocol v1.0
Specification.
The DMA control block contains the control logic that provides the following features:
•
It arbitrates the incoming requests
•
It indicates which channel is active
•
It indicates when a channel is complete
•
It indicates when an error has occurred on the AHB-Lite interface
•
It enables slow peripherals to stall the completion of a DMA cycle
•
It waits for a request to clear before completing a DMA cycle
•
It performs multiple or single DMA transfers for each request
•
It performs the supported types of DMA transfers.
15.6.2
DMA memory map
The memory map accessible by DMA is described in
Table 103
DMA memory map
Address range
Size
Peripheral
Bus matrix
master
0000_0000h - 2004_FFFFh
Reserved
2005_0000h - 2005_3FFFh
16 kB
RAM1 (replica)
M2
2005_4000h - 2005_7FFFh
16 kB
RAM1 (replica)
2005_8000h - 2005_BFFFh
16 kB
RAM1 (replica)
2005_C000h - 2005_FFFFh
16 kB
RAM1
2006_0000h - 2006_3FFFh
16 kB
RAM2
M1
2006_4000h - 2006_7FFFh
16 kB
RAM2 (replica)
APB block
AHB block
DMA control block
Configuration
control
DMA data
transfer
Requests
Stall
Mode
Active channel
Channel done
Error
APB
memory
mapped
registers
AHB-Lite
master
interface
