User Manual 330 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Reference Manual (TRM). These documents are available from the Arm® website (www.arm.com). Please note
that downloading the ARMv6-M Architecture Reference Manual requires a registration process.
A simplified block diagram of the Cortex®-M0 is shown in
Figure 99
Simplified block diagram of the Cortex®-M0 processor
15.2.1
CPU interrupt sources
The Cortex®-M0 module processor embeds an Arm® Nested Vector Interrupt Controller (NVIC) supporting up to
32 interrupt sources and 1 not-maskable interrupt (NMI) source, with each one having a unique exception
number and a dedicated memory address input.
The NVIC interrupt sources comes from several CPUS resources:
•
DMA controller
•
D
TIMER
(1, 2, 3)
•
WDT
•
GPIOs (0, 1)
•
PMBus
•
I
2
C
•
UART
•
OTP module
•
Control module
The following interrupts table (
) is supported by Arm® Cortex®-M0. All interrupt sources are considered
to be synchronized with the Arm® clock domain, in particular if some of those are pulsed, then the pulse should
be larger than four Arm® clock domain cycles. All interrupt sources need to be enabled in the NVIC before being
used, with the exception of the NMI.
Interrupts generated outside the CPUS module are defined as external.
Power management interface
Interrupt
requests and
NMI
Connection
to debugger
Cortex_M0
Bus interface
Memory and
peripherals
Internal bus system
AHB LITE bus
interface unit
Wakeup
interrupt
controller
(WIC)
Nested
vector
interrupt
controller
(NVIC)
Processor
core
Debug
subsystem
JTAG /
serial-wire
debug
interface
