User Manual 328 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
15
Central processing unit subsystem
This chapter describes the CPU subsystem (CPUS) and describes the relevant register settings in more detail.
The XDPP1100 CPUS block and bus interconnections diagram is shown in
Figure 98
CPUS block diagram
The XDPP1100 CPUS is based on a multilayer Arm® AMBA® bus protocol, in which two AHB masters (Cortex®-M0
and DMA) access all peripherals through an Arm® bus matrix. The main features of the bus matrix are:
•
It allows concurrent access when the target peripherals are different
•
It provides arbitration (round-robin)
•
It implements a default slave for out-of-memory accesses
•
It is silicon proven on thousands of devices (Arm® IP)
The CPUS uses an AMBA® AHB bus protocol for data access on memories (RAM, ROM, and OTP) and an AMBA®
advanced peripheral bus (APB) protocol for peripheral register configuration.
The CPU is an Arm® Cortex®-M0, which executes the application code from ROM/OTP with FW variables in RAM.
