User Manual
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V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Fault handler
shows example timing for these two cases.
Figure 84
Immediate (non-t2) vs. t2 aligned shutdown timing
The immediate shutdown is enabled through the following registers:
•
fault0_shut_mask_loop
for the Loop 0 faults
•
fault1_shut_mask_loop
for the Loop 1 faults
•
fault_shut_mask_com
for the common faults
Registers
fault0_shut_mask_loop
and
fault1_shut_mask_loop
are programmed by FW based on the PMBus
fault RESPONSE commands.
The t2-aligned shutdown is enabled through the following registers:
•
fault0_t2_shut_mask_loop
for the Loop 0 faults
•
fault1_t2_shut_mask_loop
for the Loop 1 faults
Register
faultX_t2_shut_mask_loop
is programmed through the PMBus command FW_CONFIG_FAULTS bits
[199:168]. The t2-aligned shutdown is not available for common fault shutdown.
When a shutdown-enabled fault occurs, the event is registered as fault0_shut, fault1_shut or faultcm_shut
based on the fault type:
•
fault0_shut and faultcm_shut turn off the Loop 0 PWM outputs
•
fault1_shut and faultcm_shut turn off the Loop 1 PWM outputs
The status of the shutdown signals is available on the read-only register
fault_shut_bus
.
Fault events remain registered until cleared by FW, typically after the FW has completed its shutdown tasks
(e.g., disable unnecessary modules, reset target voltage, etc.). The following registers are used for clearing the
faults:
•
fault0_shut_clr_loop
clears the Loop 0 shutdown event
•
fault1_shut_clr_loop
clears the Loop 1 shutdown event
•
fault_shut_clr_com
clears the common shutdown event
•
fault_shut_clr_all
clears all shutdown events
9.6
Fault pin mapping
The 40-pin version of the XDPP1100 provides two GPIO-based fault pins:
•
FAULT1
•
FAULT2
PWM Ramp
PWM FET
SR FET
t1
t2
Shutdown Fault
Non-t2 shutdown timing
t2 shutdown timing
