Design Guide
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V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
ZCD pin-related design
12
ZCD pin-related design
ZCD pin filter capacitor C
ZCD
, ZCD series resistor R
ZCD,1
and ZCD shunt resistor R
ZCD,2
are connected based on the
connections shown in
ZCD
R
ZCD,2
R
ZCD,1
N
a
C
ZCD
Figure 15
ZCD pin, C
ZCD,
R
ZCD1
and R
ZCD2
connections
C
ZCD
is mainly for ZCD pin noise-filtering, so a fixed value can generally be used for different designs. C
ZCD
= 47 pF
is selected in this design example.
Note:
QR first valley switching of the MOSFET drain voltage can be achieved with t
ZCDPD
parameter fine-
tuning based on
Section 18.2
Initial t
ZCDPD
= 350 ns
can be used for powering-up of the system
before the fine-tuning.
Apart from zero crossing detection, the ZCD pin is also used to measure the reflected input voltage signal when
the MOSFET is turned on, and to measure the reflected output voltage signal when the MOSFET is turned off
afterward. Hence, it is important to select the correct R
ZCD,1
and R
ZCD,2
values, which can cover the necessary
measurement range, not only for normal conditions but also for protected conditions.
The recommended minimum ZCD series resistance R
ZCD,1,min
and maximum ZCD series resistance R
ZCD,1,max
are
defined as:
𝑅
𝑍𝐶𝐷,1,𝑚𝑖𝑛
= −
𝑁
𝑎
𝐼
𝐼𝑉,𝑚𝑎𝑥,𝑉𝑖𝑛𝑂𝑉
∙ 𝑁
𝑝
∙ [ 𝑉
𝑖𝑛𝑂𝑉(𝑝𝑘)
+
𝑉
𝐼𝑁𝑃𝐶𝐿𝑁,𝑚𝑖𝑛
∙ 𝑁 ∙ (𝑉
𝑜𝑢𝑡𝑂𝑉
+ 𝑉
𝑑
)
𝑉
𝑍𝐶𝐷𝑆𝐻,𝑚𝑎𝑥,𝑉𝑜𝑢𝑡𝑂𝑉
]
(32)
𝑅
𝑍𝐶𝐷,1,𝑚𝑎𝑥
= −
𝑁
𝑎
𝐼
𝐼𝑉,𝑚𝑖𝑛,𝑉𝑖𝑛𝑈𝑉
∙ 𝑁
𝑝
∙ [ 𝑉
𝑖𝑛𝑈𝑉(𝑝𝑘)
− ∆𝑉
𝑖𝑛,𝐻𝐹,𝑟𝑖𝑝𝑝𝑙𝑒,𝑒𝑠𝑡
+
𝑉
𝐼𝑁𝑃𝐶𝐿𝑁,𝑚𝑎𝑥
∙ 𝑁 ∙ (𝑉
𝑜𝑢𝑡𝑂𝑉
+ 𝑉
𝑑
)
𝑉
𝑍𝐶𝐷𝑆𝐻,𝑚𝑖𝑛,𝑉𝑜𝑢𝑡𝑂𝑉
]
(33)
Where:
V
inOV(pk)
and V
inUV(pk)
are respectively √2 times V
inOV
and √2 times V
inUV
.
I
IV,max,VinOV
and I
IV,min,VinUV
are respectively the recommended maximum ZCD pin negative clamping current for V
inOV
sensing and minimum ZCD pin negative clamping current for V
inUV
sensing.
V
ZCDSH,max,VoutOV
and V
ZCDSH,min,VoutOV
are respectively the recommended maximum and minimum ZCD pin voltage
sensing levels for V
outOV
sensing.
V
INPCLN,max
and V
INPCLN,min
are respectively the maximum and minimum ZCD pin negative clamping voltages.
∆V
in,HF,ripple,est
is the estimated difference between the V
inUV(pk)
level and the high-frequency ripple minimum
voltage level at the peak of AC input half sine wave. As a rule of thumb, it can be assumed to be between 25 V
and 30 V.
Taking I
IV,max,VinOV
= -3.1 mA, I
IV,min,VinUV
= -0.15 mA, V
ZCDSH,max,VoutOV
= 2.6 V, V
ZCDSH,min,VoutOV
= 2.35 V, V
INPCLN,max
= -0.22 V,
V
INPCLN,min
= -0.14 V, and ∆V
in,HF,ripple,est
= 27.5 V,
