User Manual
659
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
21.2.1
Block Diagram
shows all functional relevant interfaces associated with the SSC Kernel.
Figure 176 SSC Interface Diagram
21.3
Functional Description
21.3.1
SSC1 and SSC2 Mode Overview
The SSC supports full-duplex and half-duplex synchronous communication up to 20 MBaud (@ 40 MHz
module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from
an external master (Slave Mode). Data width, shift direction, clock polarity, and phase are programmable. This
allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered.
A 16-bit baud-rate generator provides the SSC with a separate serial clock signal.
The SSC can be configured in a very flexible way, so it can be used with other synchronous serial interfaces,
can serve for master/slave or multimaster interconnections or can operate compatible with the popular SPI
interface. Thus, the SSC can be used to communicate with shift registers (I/O expansion), peripherals (e.g.
EEPROMs, etc.) or other controllers (networking). The SSC supports half-duplex and full-duplex
communication. Data is transmitted or received on lines TXD and RXD, normally connected with pins MTSR
(Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line
MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally
connected to pin SCLK.
SSC
Module
(Kernel)
EIR
TIR
Clock
Control
Address
Decoder
RIR
Sl
av
e
f
hw_clk
SCLK
SCLKA
SCLKB
Ma
st
er
SCU_DM
Interrupt
Control
Module
Product Interface
AHB Interface
P0.x
P1.x
P2.x
Port
Control
SSC_interface_overview.vsd
Ma
st
er
MRSTA
MRSTB
MTSR
Sl
av
e
MTSRA
MTSRB
MRST
