Application Note
5 of 19
001-87564 Rev.*D
2021-06-01
A Design Guide to SPI F-
RAM™ Processor Companion
- FM33256B
Processor Companion Features
r e s t r i c t e d
4
Processor Companion Features
The FM33256B device integrates all the necessary processor supervisor features that a designer may need.
The companion features include:
•
System Power-On Reset (POR) with
RST
̅̅̅̅̅
pin
−
Low -Voltage Detect
−
Watchdog
−
Manual reset
•
Early power-fail warning
•
Event counters
•
Lockable serial number
The following sections describe each of these in detail.
4.1
System Power-On Reset with RST
̅̅̅̅̅
pin
The FM33256B product provides a processor-reset signal when the system powers up and whenever a system
fault or manual override (manual hardware reset) occurs. The
RST
̅̅̅̅̅
pin is primarily used to drive a reset to the
processor, but can be used as an input to provide a hardware reset to the system. The
RST
̅̅̅̅̅
pin does not reset or
clear any FM33256B internal registers.
There are two trigger sources that can drive reset LOW: Low Voltage (LV) Detect circuit and the Watchdog Timer
as shown in
Figure 3
Reset Trigger Sources
At power-up, the
RST
̅̅̅̅̅
pin is driven LOW as V
DD
rises toward its nominal operating value. The point at which the
RST
̅̅̅̅̅
pin is released is determined by V
TP
(Voltage Trip Point), an internal trip voltage that is always compared to
V
DD
. The internal pull-up resistor (approximately 150 k
Ω
) on the
RST
̅̅̅̅̅
pin eliminates the need for an external
resistor. When tripped, the reset circuit times out after approximately 65 ms (30 ms minimum, 100 ms
maximum). You may set V
TP
(2 bits, VTP1, VTP0 in register 18h) to one of four values: 2.6 V, 2.75 V, 2.9 V, or 3.0 V.
The other source of trigger for the
RST
̅̅̅̅̅
pin is the watchdog timer, a free-running, user-programmable timer that
can be set to time out as soon as 60 ms or as long as 1.8 seconds. The timer settings are stored in nonvolatile
registers (registers 0Bh and 0Ch), so there is no need to reinitialize these values or the trip voltage setting again.
The watchdog timer is controlled by the enable bit WDE (register 0Ch, bit 7). The Watchdog Timer works as a
window timer which allows for a delayed start.
There are two ways for the watchdog timer to trigger a reset. First, the Early Watchdog Timer Fault (EWDF in
register 09h, bit 7) forces a reset condition when a restart occurs too early (before the programmed start time
(register 0Bh) for the Watchdog Timer window is reached). Second, the Late Watchdog Timer Fault (LWDF)
RST
V
DD
WDE
-
+
V
DD
V
TP
Watchdog
Timer
Lockout
~ 150K
LV Detect
