Application Note
10 of 19
001-87564 Rev.*D
2021-06-01
A Design Guide to SPI F-
RAM™ Processor Companion
- FM33256B
Power Cycle Considerations
r e s t r i c t e d
•
Set the Read (R bit in register 00h, bit 0) which takes a snapshot of the RTC registers (assumes R bit is
previously at logic 0).
•
Issue the Read Processor Companion command (RDPC = 0x13), starting at the address 02h, and read seven
RTC bytes (02h
–
08h).
•
Clear the R bit to prepare for the next RTC read.
6
Power Cycle Considerations
To protect the F-RAM from corrupting the data during power cycles, it is recommended that
the MCU’s SS
̅̅̅
(SPI
Slave Select) control pin be held inactive as V
DD
powers up and powers down. In many cases, this may be as
simple as a pull-
up resistor R1 on the MCU’s o
utput pin that drives the FM33256B
CS
̅̅̅̅
(Chip Select) pin. As the
system microcontroller powers up, its outputs will tristate before the power supply reaches sufficient voltage
to turn various internal circuits on, thereby allowing the pull-up resistor to keep the signal at V
DD
. Similarly, at
power-down, the V
DD
voltage reaches a point where it allows
the outputs to “let go”, again allowing the pull
-up
resistor to do its job. For more information, refer to the application note
AN302 - F-RAM SPI Read & Write and
Data Protection During Power Cycles
Apart from
CS
̅̅̅̅
, you should also consider the V
DD
power-up ramp rate, power-down ramp rate, and power-up to
first access specifications. The power-up ramp rate should be slower than 50 µs/V and the power-down ramp
rate should be slower than 100 µs/V. FM33256B keeps the
RST
̅̅̅̅̅
pin LOW for t
RPU
time at power-up (V
DD
> V
TP
).
Therefore, you should wait for 100 ms (max) before the device can be accessed at power-up.
