7.3
Reset generation (ROT signal)
Reset output pin ROT
The reset output pin ROT is an open drain structure. As soon as a reset condition occurs, the device pulls the
ROT pin below
V
ROT,low
. Once the internal reset signal is released, an internal pull-up current pulls the ROT pin
towards the microcontroller supply voltage
V
IOVDD
. An external pull-up resistor can be connected between the
ROT and IOVDD pins to speed up the transition. As soon as all events leading to the reset are cleared and the
reset delay time expires, the device releases the internal reset signal.
Reset events
Different internal events can trigger a reset signal, see
for details. Depending on the severity of the
error event the device triggers a reset of the following types:
•
soft reset: the device forces the ROT pin "low", remains in ACTIVE state and keeps all supply voltages on
•
hard reset: the device forces the ROT pin "low", enters FAULT state and turns all supply voltages off
7.3.1
Electrical characteristics ROT
Table 19
Electrical characteristics ROT
T
j
= -40°C to 150°C;
V
R1VSx
= 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or condition Number
Min.
Typ.
Max.
Reset output ROT
Pull-up current
I
ROT,high
-180
-120
–
µA
V
ROT
≤ 2.0V
P_7.3.1.1
Output level "low"
V
ROT,low
–
–
0.4
V
V
IOVDD
= 5.0 V;
I
ROT
= 3.5 mA
P_7.3.1.2
Output level "low"
V
ROT,low
–
–
0.4
V
V
IOVDD
=3.3 V;
I
ROT
= 3.5 mA
P_7.3.1.3
Output fall time
t
ROT,fall
–
–
25
ns
C
ROT,load
= 50 pF
P_7.3.1.5
Reset timing
Reset cycle time
t
cycle
–
10
–
µs
–
P_7.3.1.6
Reset delay time adjustment
range
t
RD
20
–
2000
t
cycle
–
P_7.3.1.7
Reset delay time default
value
–
100
–
t
cycle
P_7.3.1.8
22
The default configuration for the reset contributor might not generate a reset at the first start up of the
device.
OPTIREG
™
PMIC TLF30681QVS01
Power management IC
Microcontroller interface and supervisory functions
Datasheet
63
Rev. 1.0
2020-04-08
