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Infineon OPTIREG TLF30681QVS01, Manual

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Infineon OPTIREG TLF30681QVS01 Manual Download Page 129

10

Application information

Note:

The following information is given as an example for the implementation of the device only and shall

not be regarded as a description or warranty of a certain functionality, condition or quality of the

device.

Logic

SMPR

Buck1

Feedback

SPI

ENABLE

ENABLE

Fault 

Manager

V_S (T30)

TM1

AG2

WDI

SDO

SDI

SCL

SCS

ENA

R1VSx

Window

 Watchdog

Reset Generator

INT

ROT

INTERRUPT 

Generator

Bandgap 2

 for V- Mon.

Bandgap 1

SMPR

Buck2

V

Buck2

Feedback

R2SWx

R2PGx

R2FB

V

Buck1

R1SWx

R1PGx

R1FB

NC

R2VS1x

R1BTS

UV/OV-Monitoring/

Enable Handling

Internal 

Supply

SPI_DataIn

SPI_Clock

SPI_ChipSelect

SPI_DataOut

Watchdog_TriggerIn

µC_Reset

Interrupt

ExtRail1_Feedback

ExtRail1_Enable

VM1EN
VM1FB

ExtRail2_Feedback

ExtRail2_Enable

VM2EN
VM2FB

Clock 

Generation

SYNCO

SYNCI

SYNC_In

SYNC_Out

MPS

R3SW

SMPR

Boost

R3PG

V

Boost1

Feedback

R3FB

AG3

IOVDD

AG4

AG5

R1BTSV

Interface_supply

NC

TM2

AG1

Buck1 

Driver 

Supply

AG6

C

Buck1

_1

C

Buck1_2

C

Buck1_3

L

Buck1

C

Buck1_BST

C

Boost1_1

C

Boost1_2

L

Boost1

L

Buck2

C

Buck2

_1

C

Buck2_2

Figure 24

Application diagram

Note:

This figure is a simplified example of an application circuit. The function must be verified in the

application.

Table 30

Recommended values for the passive components in 

Figure 24

Name

Value
(typical)

Comments

L

Buck1

3.3 µH

Buck1 inductor:
Use an inductor with a saturation current above the Buck1 overcurrent protection

threshold 

I

R1,OCP

.

C

Buck1_1

33 µF

Buck1 output capacitor 1:
Use a ceramic capacitor in X7R material with a voltage rating of 6.3 V or higher.
Place this capacitor close to the R2VSx input of Buck2 and connect it between the R2VSx

and R2PGx pins directly.

OPTIREG

™

 PMIC TLF30681QVS01

Power management IC

Application information

Datasheet

129

Rev. 1.0

2020-04-08

Summary of Contents for OPTIREG TLF30681QVS01

Page 1: ...Driver Assistance Systems ADAS The device consists of a battery connected buck regulator Buck1 providing 3 3 V to external loads and to two low voltage post regulators The first post regulator Buck2 p...

Page 2: ...ng channels can be used to control and monitor external LDOs or external DC DC switching regulators Type Package Marking TLF30681QVS01 PG VQFN 48 TLF30681 S01 OPTIREG PMIC TLF30681QVS01 Power manageme...

Page 3: ...s Buck1 24 4 2 Post regulator step down converter Buck2 25 4 2 1 Functional description Buck2 25 4 2 2 Electrical characteristics Buck2 27 4 2 3 Typical performance characteristics Buck2 29 4 3 Post r...

Page 4: ...7 1 Microcontroller interface supply IOVDD pin 52 7 1 1 Electrical characteristics microcontroller interface supply 54 7 2 Serial peripheral interface SPI 55 7 2 1 SPI introduction 55 7 2 2 SPI write...

Page 5: ...egister B2VCTRLN 101 9 1 4 General registers 102 9 1 4 1 Register PROTCFG 102 9 1 4 2 Register WWDSCMD 103 9 1 5 Event status registers 104 9 1 5 1 Register GSF 104 9 1 5 2 Register SYSSF0 106 9 1 5 3...

Page 6: ...isters 126 9 1 7 1 Register HWDECT0 127 9 1 7 2 Register DEVID 128 10 Application information 129 11 Package information 131 Revision history 132 Disclaimer 133 OPTIREG PMIC TLF30681QVS01 Power manage...

Page 7: ...toring Enable Handling Internal Supply SPI_DataIn SPI_Clock SPI_ChipSelect SPI_DataOut Watchdog_TriggerIn C_Reset Interrupt ExtRail1_Feedback ExtRail1_Enable VM1EN VM1FB ExtRail2_Feedback ExtRail2_Ena...

Page 8: ...FB 47 SDI 38 22 R2FB 21 AG4 20 R1FB 19 AG3 18 AG2 17 AG1 16 R1BTS 15 R1SW3 14 R1SW2 23 R2PG1 34 IOVDD 33 MPS 32 TM1 31 R3FB 30 R3PG1 29 R3SW1 28 R2VS2 27 R2VS1 26 R2SW2 35 SYNCO R1PG1 10 R1VS3 9 R1VS2...

Page 9: ...between this pin and ground An EMC filter is recommended 9 R1VS3 High voltage regulator supply voltage pin 3 Connect this pin in parallel with R1VS1 and R1VS2 and then to the supply battery voltage v...

Page 10: ...utput capacitor ground terminal to ground 24 R2PG2 Pre regulator power ground pin 2 Connect this pin in parallel with R2PG1 and then to the Buck2 output capacitor ground terminal to ground 25 R2SW1 Po...

Page 11: ...gulators The feature needs to be enabled via SPI If the pin is not used then leave it floating 37 SDO Serial peripheral interface signal data output SPI signalling port connect this pin to the SPI por...

Page 12: ...rated by the optional external voltage regulator 1 If the optional external regulator is not used then connect this pin to ground 48 VM2FB Input for optional external voltage monitoring rail 2 Connect...

Page 13: ...13 AG2 VAG2 0 3 0 3 V P_3 1 14 AG3 VAG3 0 3 0 3 V P_3 1 15 AG4 VAG4 0 3 0 3 V P_3 1 16 AG5 VAG5 0 3 0 3 V P_3 1 17 AG6 VAG6 0 3 0 3 V P_3 1 18 SYNCI VSYNCI 0 3 6 0 V P_3 1 19 SYNCO VSYNCO 0 3 6 0 V P...

Page 14: ...R2SW2 0 3 7 0 V P_3 1 40 R2PG1 VR2PG1 0 3 0 3 V P_3 1 41 R2PG2 VR2PG2 0 3 0 3 V P_3 1 42 R2FB VR2FB 0 3 7 0 V P_3 1 43 R3SW1 VR3SW1 0 3 7 0 V P_3 1 44 R3PG1 VR3PG1 0 3 0 3 V P_3 1 45 R3FB VR3FB 0 3 7...

Page 15: ...3 2 Functional range Table 2 Functional range Parameter Symbol Values Unit Note or condition Number Min Typ Max Supply voltage range for normal operation VR1VSx 5 0 35 V 5 P_3 2 1 Supply voltage range...

Page 16: ...ad RthJSP 13 1 18 0 K W JEDEC 1s0p P_4 3 2 Junction to ambient RthJA 37 K W 8 P_4 3 3 Note This thermal data was generated in accordance with JEDEC JESD51 standards For more information visit www jede...

Page 17: ...C 9 V VR1VSx 25 V no load watchdog disabled P_3 4 1 DISABLED state Iq DIS 13 17 5 A Tj 85 C 9 V VR1VSx 25 V P_3 4 2 DISABLED state Iq DIS 11 13 5 A Tj 25 C VR1VSx 13 5 V P_3 4 3 FAULT state Iq FLT 1...

Page 18: ...t current DISABLED state quiescent current Iq versus supply voltage VR1VSx LOCKED state quiescent current Iq versus supply voltage VR1VSx OPTIREG PMIC TLF30681QVS01 Power management IC General product...

Page 19: ...he output voltage Internal compensation allows for fast loop performance across a wide range of output capacitance No external tuning of the loop is required The device supports ceramic capacitors as...

Page 20: ...ile the external voltage compensation loop regulates the output voltage The compensation loop can operate with a variety of power stages For information on the selection of the external components see...

Page 21: ...and it generates an interrupt If the junction temperature continues to rise and exceeds the overtemperature shutdown threshold then the converter shuts down and generates a thermal shut down TSD event...

Page 22: ...ow side switch on resistance RDSOn R1LS 95 m 5 0 V VR1VSx 35 V P_4 1 2 42 Low side switch on resistance derated RDSOn R1LS D R m 3 7 V VR1VSx 5 0 V P_4 1 2 43 Overcurrent protection threshold IR1OCP 4...

Page 23: ...ctive inductance LR1 2 64 3 3 4 0 H 10 P_4 1 2 33 Effective output capacitance CR1 75 100 240 F 10 11 P_4 1 2 35 ESR of output capacitance RR1C 0 5 30 m P_4 1 2 36 10 For additional information on the...

Page 24: ...1 Buck1 output voltage VR1FB versus load current IR1IOUT Buck1 output voltage VR1FB versus supply voltage VR1VSx drop out region OPTIREG PMIC TLF30681QVS01 Power management IC Power converters and pow...

Page 25: ...nt threshold at the end of the switching period then the device does not turn on the high side switch in the subsequent switching period This allows the device to work as a constant current source If...

Page 26: ...tion in order to allow the microcontroller to verify correct detection for the specific application and to differentiate the result from a possible fault present on the PCB To indicate to the device t...

Page 27: ...rent timeout tR2 OCP 95 100 115 s P_4 2 2 20 Minimum on time tR2SWx 64 79 87 ns Minimum on time for internal high side control signal The actual on time on the R2SWx pins depends on the application de...

Page 28: ...eter Symbol Values Unit Note or condition Number Min Typ Max ESR of output capacitance RR2C 0 5 30 m P_4 2 2 31 14 Effective capacitance including derating over the temperature range bias voltage and...

Page 29: ...cal performance characteristics Buck2 Buck2 output voltage VR2FB versus load current IR2IOUT OPTIREG PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 29 Rev 1 0 2...

Page 30: ...a short circuit directly However indirect protection via an undervoltage protection and current limitation of the front end converter Buck1 is available Automatic use detection The integrated automati...

Page 31: ...t detection threshold IR3 OCP 740 820 900 mA P_4 3 2 5 Overcurrent timeout tR3 OCP 170 220 260 s P_4 3 2 6 External power stage components Effective inductance LR3 3 8 6 8 9 8 H 15 P_4 3 2 8 Effective...

Page 32: ...al performance characteristics Boost1 Boost1 output voltage VR3FB versus load current IR3IOUT OPTIREG PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 32 Rev 1 0...

Page 33: ...r the specific application and differentiate the result from a possible fault condition on the PCB To indicate to the device that the application does not require a voltage monitor connect the respect...

Page 34: ...required at the IOVDD pin in order to operate the digital outputs of the device see Microcontroller interface supply IOVDD pin 5 1 1 Electrical characteristics supply voltages Table 9 Electrical chara...

Page 35: ...on where a low to high transition or a high to low transition of the enable signal is considered an enable event Upon detection of an enable event the device generates an interrupt SYSSF1 QM ENA Depen...

Page 36: ...to the default value The device can therefore only recognize an ENA event in DISABLED state if the ENA pin has a low to high transition 5 2 2 Electrical characteristics enable Table 10 Electrical char...

Page 37: ...ypical performance characteristics enable ENA pin input voltage thresholds VENA versus junction temperature Tj OPTIREG PMIC TLF30681QVS01 Power management IC Central functions Datasheet 37 Rev 1 0 202...

Page 38: ...is reached For example during ramp up of Buck1 the device waits until its output voltage exceeds the undervoltage threshold and until the rise time tBuck1 has elapsed before it initiates the ramping...

Page 39: ...eset signal with a configurable delay once the microcontroller supply voltage is within the operating band for a selectable time period DEVCFG0 RESDEL For generation of the microcontroller reset signa...

Page 40: ...otherwise specified Parameter Symbol Values Unit Note or condition Number Min Typ Max Internal device startup time tSTARTUP 300 s P_5 3 1 Output voltage rise time Buck1 tBUCK1 640 s VBUCK1 3 3 V P_5...

Page 41: ...r Spread spectrum Modulator Clock Synchroni zation fMain SYNCI Main Clock Selector fMain Buck1 Selector fR1 Buck2 Selector Boost1 Selector 180 fR2 fR3 SYNCO Selector fSYNCO 180 180 Figure 6 Clock gene...

Page 42: ...chronization output is disabled by default The synchronization output can be enabled via SPI CLKCFG0 allows to adjust the phase shift between the individual converters The phase shift is defined betwe...

Page 43: ...ase delay between SYNCIN and switching edges 30 ns P_5 4 11 Output voltage settling time tSync 50 s P_5 4 12 Synchronization output signal SYNCO18 Output level high VSYNCO high 0 7 VIOVDD IIOVDD 7 mA...

Page 44: ...pical performance characteristics frequency generation Switching frequency fMAIN versus junction temperature Tj OPTIREG PMIC TLF30681QVS01 Power management IC Central functions Datasheet 44 Rev 1 0 20...

Page 45: ...ground detection time then the device generates a short to ground event A short to ground event on IOVDD triggers a hard reset in the device and the SYSSF0 QM IOVDDUV ROT VIOVDD 1 V VIOVDD OV VIOVDD U...

Page 46: ...current flowing into pin unless otherwise specified Parameter Symbol Values Unit Note or condition Number Min Typ Max IOVDD undervoltage hysteresis VIOVDD UV Hys 0 4 2 25 P_5 6 4 Deglitching time tIOV...

Page 47: ...xecutes appropriate according actions see State transitions and trigger signals When the device enables a power rail it activates the respective voltage monitoring automatically For information on the...

Page 48: ...g on the internal root cause the device sets SYSSF0 QM BGFLT1 or SYSSF0 QM BGFLT2 6 1 5 Electrical characteristics voltage monitoring Table 14 Electrical characteristics voltage monitoring Tj 40 C to...

Page 49: ...2 25 P_6 1 5 22 Deep undervoltage threshold VBuck2 DUV 38 40 42 P_6 1 5 23 Deep undervoltage hysteresis VBuck2 DUV Hy s 0 8 3 15 P_6 1 5 24 Deglitching time tBuck2 deg 8 20 s P_6 1 5 25 Short to groun...

Page 50: ...ferenced to VM2 nominal reference voltage VVM2FB nom P_6 1 5 52 Undervoltage hysteresis VVM2 UV Hys 0 4 2 25 P_6 1 5 54 Deglitching time tVM2 deg 8 20 s P_6 1 5 55 Short to ground detection time tVM2...

Page 51: ...ges with respect to ground positive current flowing into pin unless otherwise specified Parameter Symbol Values Unit Note or condition Number Min Typ Max Overtemperature warning threshold Tj MONOT WRN...

Page 52: ...if required Series Protection resistors C SPI SPI Reset Control Window Wacthdog Interrupt Generator Reset Generator ROT WDI SDO SDI SCL SCS INT IOVDD TRIGGER OUTPUT INTERRUPT INPUT C TLF30681 Figure 8...

Page 53: ...WDI SYNCI SYNCO OPTIREG PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 53 Rev 1 0 2020 04 08...

Page 54: ...otherwise specified Parameter Symbol Values Unit Note or condition Number Min Typ Max Microcontroller interface Supply voltage VIOVDD 3 0 5 5 V P_7 1 1 1 Supply current IIOVDD 2 5 mA VIOVDD 3 3 V SDO...

Page 55: ...SPI response for read operations consists of the following parts command bit CMD 6 status bits S0 S5 8 data bits D0 D7 parity bit P For a write operation the data read on SDI is looped back via SDO A...

Page 56: ...ores the data sets the SPI status SPISF LEN and generates an interrupt If a read operation with an incorrect number of SPI clock cycles occurs then the device sets the SPI status SPISF LEN and generat...

Page 57: ...bytes 1 ABH 2 EFH 3 56H 4 12H written into the PROTCFG register The respective SPI write operations must be atomic so that they are not interrupted by an SPI write operation to a different register Re...

Page 58: ...es the transition request without generating an interrupt The device executes the change in configuration of output rails 7 2 4 Configuration of Buck2 output voltage via SPI The output voltage of Buck...

Page 59: ...SPI_clkr E t SPI_clkf F t SPI_su G t SPI_hi H t SPI_a I t SPI_v J t SPI_fl K t SPI_dis L t SPI_lead M t SPI_lag N t SPI_td O t SPI_csf P t SPI_csr Q t SPI_dr J Figure 10 SPI timing OPTIREG PMIC TLF306...

Page 60: ..._7 2 5 8 Pull up current ISCL 180 55 A VIOVDD 5 0 V P_7 2 5 9 Input capacitance CSCL 4 15 pF 21 P_7 2 5 10 SPI data input SDI Valid input level high VSDI high 0 7 VIOVDD VSDI increasing P_7 2 5 11 Val...

Page 61: ...2 5 30 CLK_SPI lag time tSPI_lag 50 ns P_7 2 5 31 SPI chip select SCS rise time tSPI_csr 200 ns tSPI_lead 100 ns P_7 2 5 32 SPI chip select SCS rise time tSPI_csr 0 2 tSPI_lead ns tSPI_lead 100 ns P_...

Page 62: ...pecified Parameter Symbol Values Unit Note or condition Number Min Typ Max SPI data output SDO disable time tSPI_dis 100 ns CSDO load 50 pF P_7 2 5 43 Sequential transfer delay tSPI_td 350 ns P_7 2 5...

Page 63: ...reset the device forces the ROT pin low enters FAULT state and turns all supply voltages off 7 3 1 Electrical characteristics ROT Table 19 Electrical characteristics ROT Tj 40 C to 150 C VR1VSx 3 7 V...

Page 64: ...lling the interrupt line low for at least tINT interrupt min pulse width after an internal interrupt condition occurs The interrupt line will be driven high if all of the GSF register flag s has have...

Page 65: ...t POR HIGH LOW FSM State t Internal interrupt request SPI service done t POR ACTIVE HIGH LOW t Interrupt line t SPI service done SPI service done HIGH LOW t HIGH LOW t INT not serviced flag previously...

Page 66: ...all voltages with respect to ground positive current flowing into pin unless otherwise specified Parameter Symbol Values Unit Note or condition Number Min Typ Max Interrupt signal INT Output level hi...

Page 67: ...ified Parameter Symbol Values Unit Note or condition Number Min Typ Max Interrupt low timeout tINTTO 270 300 330 s ROT signal for the microcontroller must be released ROT high P_7 4 1 6 Minimum interr...

Page 68: ...uration is the triggering via SPI The duration of the open window and closed window cycles can be modified according to the application needs combination of cycle time and number of cycles for open wi...

Page 69: ...ndow watchdog error is greater than 0 then valid WWD triggering decrements the window watchdog error counter by 1 If no valid triggering occurs during the open window then the window watchdog recogniz...

Page 70: ...ice requires at least two high samples followed by two low samples for a valid trigger signal Whether the triggering is valid the window watchdog decides at the time of the second consecutive low samp...

Page 71: ...configuration The maximum duration of the long open window is fixed On valid WWD triggering the window watchdog terminates the long open window 3 The window watchdog starts the closed window 4 The clo...

Page 72: ...detect valid triggering during ACTIVE state it generates a soft reset The device sets ROT to low while the output voltages of the post regulators remain on 3 After the soft reset the pin ROT turns hig...

Page 73: ...n valid triggering the window watchdog terminates the open window The duration of the open window depends on when the triggering occurs Due to the valid WWD triggering the window watchdog starts a clo...

Page 74: ...indow so the microprocessor gets the opportunity to synchronize to the window watchdog period 3 During this open window the window watchdog waits for valid triggering On valid triggering the window wa...

Page 75: ...o the microprocessor gets the opportunity to synchronize to the window watchdog period 3 During this open window the window watchdog waits for valid triggering On valid triggering the window watchdog...

Page 76: ...ng during the initialization period The programming mode can be enabled by pulling the MPS pin high In programming mode the reset generation to the microcontroller is modified so that fault events of...

Page 77: ...ote or condition Number Min Typ Max MPS pin Valid input level high VMPS high 2 4 V VMPS increasing P_7 8 0 1 Valid input level low VMPS low 0 8 V VMPS decreasing P_7 8 0 2 Input hysteresis VMPS hys 35...

Page 78: ...e event Timer expired Buck1 OFF Buck2 OFF VM1 VM2 OFF LOCKED ROT LOW Fault has occured three times and DEVCFG0 ENA_CONFIG 0 Enable event SPI Goto to LOCKED and DEVCFG0 ENA_CONFIG 0 Buck1 Buck2 VM1 IOV...

Page 79: ...e and expects configuration from the microcontroller In DISABLED state the device resets the content of all registers The device needs to be configured again during the ACTIVE state FAULT On detection...

Page 80: ...nt state SEL The function is operating as configured via SPI during the mode transition or within the current operation mode off The function is automatically deactivated when entering the operation m...

Page 81: ...d and ENA_CONFIG 0 ACTIVE FAULT Hard reset fault detected DISABLED ACTIVE Enable event Generate MCU reset FAULT ACTIVE FAULT timer expires Generate MCU reset FAULT LOCKED 25 Hard reset fault occurs th...

Page 82: ...nter increase X WWD counter overflow X INIT timer expired first time X INIT timer expired second time X Internal protection band gap warning X Internal protection band gap fault X IOVDD OV X IOVDD UV...

Page 83: ...irst Initialisation Error Start up with second Initialisation Error Second INIT error detected Hard Reset event is generated FSM moved to Fault state t POR HIGH LOW Device remains in Active state afte...

Page 84: ...ULT ACTIVE LOCKED t t t Device enters LOCKED state after third initialisation error if ENA LOW First INIT error detected Soft Reset event is generated FSM moved to active state after Fault time is exp...

Page 85: ...3H R0 Page 88 CLKCFG0 Clock configuration 0 01H 00H R2 Page 89 CLKCFG1 Clock configuration 1 02H 04H R2 Page 90 PROTCFG Configuration protection 03H 00H R2 Page 102 PWDCFG0 Protected watchdog configur...

Page 86: ...H R1 Page 118 VMONSTAT0 Voltage monitoring 27H 00H R1 Page 119 DEVSTAT Device state information 28H 00H R1 Page 121 PROTSTAT Protection status information 29H 01H R2 Page 122 WWDSTAT Window watchdog s...

Page 87: ...9 1 SPI register definition 9 1 1 Device configuration registers device startup default configuration OPTIREG PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 87 Rev 1 0 2020 04 08...

Page 88: ...rnal voltage monitoring 1 enable at start up 0H disabled 1H enabled Reset 1H BOOST1ENAS 5 r Boost1 enable at start up 0H disabled 1H enabled Reset 1H BUCK2ENAS 4 r Buck2 enable at start up 0H disabled...

Page 89: ...phase alignment 0H 0 phase shift 1H 180 phase shift Reset 0H PHSO 4 rw External clock synchronization phase alignment 0H 0 phase shift 1H 180 phase shift Reset 0H nu 3 r Not used SSEN 2 rw Spread spec...

Page 90: ...4 3 2 1 0 nu FREQSEL r rw Field Bits Type Description nu 7 3 r Not used FREQSEL 2 0 rw Main switching frequency 0H 1 8 MHz 1H 1 9 MHz 2H 2 0 MHz 3H 2 1 MHz 4H 2 2 MHz 5H 2 3 MHz 6H 2 4 MHz 7H 2 5 MHz...

Page 91: ...or threshold 0H 0 1H 1 FH 15 Reset 9H WWDEN 3 rwp Window watchdog enable 0 B disabled 1 B enabled 1 B nu 2 r Not used WWDTSEL 1 rwp Window watchdog trigger selection 0 B external WDI input used as WWD...

Page 92: ...6 5 4 3 2 1 0 nu CW r rwp Field Bits Type Description nu 7 r Not used CW 6 0 rwp Window watchdog closed window size 00H 0 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles 7FH 6350 watchd...

Page 93: ...6 5 4 3 2 1 0 nu OW r rwp Field Bits Type Description nu 7 r Not used OW 6 0 rwp Window watchdog open window size 00H 50 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles 7FH 6350 watchdo...

Page 94: ...dow watchdog error threshold ACTIVE 0H 0 1H 1 FH 15 Reset 9H WWDEN 3 r Window watchdog enable STATUS 0 B disabled 1 B enabled 1 B nu 2 r Not used WWDTSEL 1 r Window watchdog trigger selection ACTIVE 0...

Page 95: ...5 4 3 2 1 0 nu CW r r Field Bits Type Description nu 7 r Not used CW 6 0 r Window watchdog closed window size ACTIVE 00H 0 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles 7FH 6350 watch...

Page 96: ...5 4 3 2 1 0 nu OW r r Field Bits Type Description nu 7 r Not used OW 6 0 r Window watchdog open window size ACTIVE 00H 50 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles 7FH 6350 watch...

Page 97: ...procedure This procedure is based on the access to two individual registers writing inverted information For detailed information please refer to SPI write initiated state transition request and regul...

Page 98: ...EN 6 rw External voltage monitoring 1 enable request 0H disable 1H enable Reset 0H BOOST1EN 5 rw Boost1 enable request 0H disable 1H enable Reset 0H BUCK2EN 4 rw Buck2 enable request 0H disable 1H ena...

Page 99: ...0H VM1EN 6 rw External voltage monitoring 1 enable request 0H enable 1H disable Reset 0H BOOST1EN 5 rw Boost1 enable request 0H enable 1H disable Reset 0H BUCK2EN 4 rw Buck2 enable request 0H enable 1...

Page 100: ...nu B2VOUTF r rwhu Field Bits Type Description nu 7 4 r Not used B2VOUTF 3 0 rwhu Buck2 output voltage setting fine resolution 0H 1 30 V 1H 1 20 V 2H 1 25 V 3H 1 15 V 4H 1 10 V 5H 1 00 V 6H 1 05 V 7H...

Page 101: ...2 1 0 nu B2VOUTF r rwhu Field Bits Type Description nu 7 4 r Not used B2VOUTF 3 0 rwhu Buck2 output voltage setting fine resolution FH 1 30 V EH 1 20 V DH 1 25 V CH 1 15 V BH 1 10 V AH 1 00 V 9H 1 05...

Page 102: ...TCFG RMAP X Address 03H Configuration protection PAGE 2 Reset Value 00H 7 6 5 4 3 2 1 0 KEY rw Field Bits Type Description KEY 7 0 rw Protection key Reset 00H OPTIREG PMIC TLF30681QVS01 Power manageme...

Page 103: ...7 6 5 4 3 2 1 0 TRIG_STAT US nu TRIG r r rw Field Bits Type Description TRIG_STATUS 7 r Window watchdog last trigger received via SPI Reset 00H nu 6 1 r Not used TRIG 0 rw Window watchdog trigger comm...

Page 104: ...egister GSF GSF RMAP X Address 1AH Global status flags PAGE 0 Reset Value 00H 7 6 5 4 3 2 1 0 INTMISS nu R1VSxUV OT MON SPI MCU SYS r r rw1c rw1c rw1c rw1c rw1c rw1c Field Bits Type Description INTMIS...

Page 105: ...vent write 0 no action 1H event occurred write 1 to clear the flag Reset 0H SYS 0 rw1c System event flag SYSSF0 QM SYSSF1 QM 0H no event write 0 no action 1H event occurred write 1 to clear the flag R...

Page 106: ...0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H IOVDDOV 5 rw1c IOVDD overvoltage event 0H no event write 0 no action 1H event occurred write 1 to clear the flag Rese...

Page 107: ...n a power on reset event write 0 no action 1H device wake up on ENA event write 1 to clear the flag Reset 0H nu 4 r Not used SYNC 3 rw1c External clock synchronization fault event 0H no event write 0...

Page 108: ...OPTIREG PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 108 Rev 1 0 2020 04 08...

Page 109: ...ear the flag Reset 0H SOFTRES 6 rw1c Soft reset event 0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H nu 5 4 rw1c Not used WWDF 3 rw1c Window watchdog fault event 0H...

Page 110: ...3 2 1 0 nu WWDMISS nu r rw1c r Field Bits Type Description nu 7 4 r Not used WWDMISS 3 rw1c Window watchdog missed trigger event 0H no event write 0 no action 1H event occurred write 1 to clear the fl...

Page 111: ...0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H DUR 3 rw1c SPI duration error event Chip select signal CS low for more than 2 ms 0H no event write 0 no action 1H eve...

Page 112: ...nitoring 1 short to ground event 0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H nu 5 r Not used BOOST1STG 4 rw1c Boost1 short to ground event 0H no event write 0 no...

Page 113: ...monitoring 1 overvoltage event 0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H nu 5 r Not used BOOST1OV 4 rw1c Boost1 overvoltage event 0H no event write 0 no action...

Page 114: ...onitoring 1 undervoltage event 0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H nu 5 r Not used BOOST1UV 4 rw1c Boost1 undervoltage event 0H no event write 0 no actio...

Page 115: ...ent write 0 no action 1H event occurred write 1 to clear the flag Reset 0H nu 6 2 r Not used BUCK2OT 1 rw1c Buck2 overtemperature fault event 0H no event write 0 no action 1H event occurred write 1 to...

Page 116: ...event write 0 no action 1H event detected write 1 to clear flag Reset 0H nu 6 2 r Not used BUCK2OTW 1 rw1c Buck2 overtemperature warning event 0H no event write 0 no action 1H event occurred write 1 t...

Page 117: ...ent 0H no event write 0 no action 1H event occurred write 1 to clear the flag Reset 0H nu 3 2 r Not used BUCK2OCW 1 rw1c Buck2 overcurrent warning event 0H no event write 0 no action 1H event occurred...

Page 118: ...ature status 0 warnings PAGE 1 Reset Value 00H 7 6 5 4 3 2 1 0 MONOTW nu BUCK2OTW BUCK1OTW r r r r Field Bits Type Description MONOTW 7 r Monitoring overtemperature warning STATUS 0H no overtemperatur...

Page 119: ...tage not present 1H battery voltage undervoltage present Reset 0H BOOST1OK 4 r Boost1 STATUS 0H output rail disabled or not in total operation band 1H output rail enabled and in total operation band R...

Page 120: ...OPTIREG PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 120 Rev 1 0 2020 04 08...

Page 121: ...ernal voltage monitoring 1 enable STATUS 0H voltage is disabled 1H voltage is enabled Reset 0H BOOST1EN 5 r Boost 1 enable STATUS 0H voltage is disabled 1H voltage is enabled Reset 0H BUCK2EN 4 r Buck...

Page 122: ...KEY3OK 6 r Third protection key valid STATUS 0H key not valid 1H key valid Reset 0H KEY2OK 5 r Second protection key valid STATUS 0H key not valid 1H key valid Reset 0H KEY1OK 4 r First protection ke...

Page 123: ...ormation PAGE 2 Reset Value 00H 7 6 5 4 3 2 1 0 nu WWDECNT r r Field Bits Type Description nu 7 4 r Not used WWDECNT 3 0 r Window watchdog error counter level 0H 0 1H 1 FH 15 Reset 0H OPTIREG PMIC TLF...

Page 124: ...03H 7 6 5 4 3 2 1 0 nu MPSSTAT r r Field Bits Type Description nu 7 4 r Not used MPSSTAT 3 0 r MPS STATUS 3H device in operating mode 6H device in programming mode 9H device in test mode production t...

Page 125: ...ut voltage setting coarse resolution STATUS 0H Range 0 9 1 3 V Fine resolution is evaluated 1H 1 5 V 2H 1 8 V 3H 2 45 V 4H 3 3 V Reset 0H BUCK2VOUTF 3 0 r Buck2 output voltage setting fine resolution...

Page 126: ...9 1 7 Device information registers OPTIREG PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 126 Rev 1 0 2020 04 08...

Page 127: ...utomatic use detection 0H VM1 is not used in this application 1H VM1 is used in this application Reset 1H nu 5 r Not used BOOST1AVA 4 r Boost1 automatic use detection 0H Boost1 is not used in this app...

Page 128: ...evice identification PAGE 1 Reset Value 30H 7 6 5 4 3 2 1 0 DEVTYPE r Field Bits Type Description DEVTYPE 7 0 r Device family 30H TLF30681 device Reset 30H OPTIREG PMIC TLF30681QVS01 Power management...

Page 129: ...SYNCO SYNCI SYNC_In SYNC_Out MPS R3SW SMPR Boost R3PG VBoost1 Feedback R3FB AG3 IOVDD AG4 AG5 R1BTSV Interface_supply NC TM2 AG1 Buck1 Driver Supply AG6 C Buck1_1 C Buck1_2 C Buck1_3 LBuck1 CBuck1_BST...

Page 130: ...CBuck2_2 33 F Buck2 output capacitors 1 to 2 Use a ceramic capacitor in X7R material with a voltage rating of 6 3 V or higher LBoost1 6 8 H Boost1 inductor Use an inductor with a saturation current ab...

Page 131: ...CE WITH ISO 128 PROJECTION METHOD 1 48x 0 3 5 0 1 3 0 0 5 0 15 0 05 INDEX MARKING 0 4 x 45 Figure 25 PG VQFN 48 Green Product RoHS compliant To meet the world wide customer requirements for environmen...

Page 132: ...Revision history Revision Date Changes 1 0 2020 04 08 Datasheet created OPTIREG PMIC TLF30681QVS01 Power management IC Revision history Datasheet 132 Rev 1 0 2020 04 08...

Page 133: ...nt is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements norms and standards concerning customer s products and any use of the product...

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