Infineon MERUS MA12070P, User Manual, Page: 5 / 28

Application Note 5 of 28 V 1.0
2019-04-28
User manual for MA120xxx reference boards
Board overview
Figure 2 shows the top view of the board assembly. The board has following key features, which are indicated by
corresponding numbers marked with red.
1. PVDD power connector: connect PVDD 5 V to 18 V for MA12040(P) or connect PVDD 5 V to 26 V for
MA12070(P)
2. BTL output connection channel 0
3. BTL output connection channel 1
4. PAUDIO: signal input connector:
o
For MA12070 devices:

Pin 5: AN0A – analog input A channel 0

Pin 4: AN0B – analog input B channel 0

Pin 3: GND

Pin 2: AN1A – analog input A channel 1

Pin 1: AN1B – analog input B channel 1
o
For MA12070P devices:

Pin 5: SCK – I 2 S bit clock

Pin 4: WS – I
2
S word clock

Pin 3: GND

Pin 2: SD0 – I
2
S audio data

Pin 1: CLK – I 2 S master clock
5. PCTRL external communication:

Pin 5: SCL – I
2
C clock

Pin 4: SDA – I
2
C data

Pin 3: GND

Pin 2: /ENABLE – enable or disable the amplifier

Pin 1: /MUTE – mute or unmute the amplifier
6. MA12040, MA12040P, MA12070 or MA12070P Eximo multi-level amplifier IC
7. Buck regulator: TPS62175 – for generating 5 V supply