Document Number: 002-14826 Rev. *G
Page 50 of 65
PRELIMINARY
CYW43903
15.2 3.3V LDO (LDO3P3)
Table 26. LDO3P3 Specifications
Specification
Notes
Min.
Typ.
Max.
Units
Input supply voltage, V
in
Min. = V
o
+ 0.2V = 3.5V dropout voltage requirement
must be met under maximum load for performance
specifications.
3.0
3.6
4.8
1
1. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as
high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
V
Output current
–
0.001
–
450
mA
Nominal output voltage, V
o
Default = 3.3V.
–
3.3
–
V
Dropout voltage
At max. load.
–
–
200
mV
Output voltage DC accuracy
Includes line/load regulation.
–5
–
+5
%
Quiescent current
No load.
–
–
85
µA
Line regulation
V
in
from (V
o
+ 0.2V) to 4.8V, max. load.
–
–
3.5
mV/V
Load regulation
Load from 1 mA to 450 mA.
–
–
0.3
mV/mA
PSRR
V
in
≥ V
o
+ 0.2V, V
o
= 3.3V, C
o
= 4.7 µF, Max load,
100 Hz to 100 kHz.
20
–
–
dB
LDO turn-on time
Chip already powered up.
–
160
250
µs
External output capacitor, C
o
Ceramic, X5R, 0402,(ESR: 5 mΩ–240 mΩ), ± 10%,
10V.
1.0
2
2. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
4.7
10
µF
External input capacitor
For LDO_VDDBAT5V pin (shared with band gap)
ceramic, X5R, 0402, (ESR: 30mΩ–200 mΩ), ± 10%,
10V.
Not needed if sharing 4.7 µF VBAT capacitor with
SR_VDDBAT5V.
–
4.7
–
µF
