User Guide
32 of 67
002-32601 Rev. *C
2021-12-02
EZ-
PD™ PMG1 MCU prototyping kits guide
CY7110/CY7111/CY7112/CY7113
EZ-
PD™ PMG1 prototyping kit system design
Table 11
GPIO details for user LEDs and user buttons
Kit
User LED GPIO
User button GPIO
CY7110
P2.1
P2.0
CY7111
P2.1
P2.0
CY7112
P1.3
P1.2
CY7113
P5.5
P3.3
3.3.4
10-pin SWD header
The 10-pin SWD/JTAG connector is a programming and debug interface connector. The header is pin-
compatible with all standard 10-pin SWD/JTAG interfaces
, and supports Infineon’s MiniProg4
program and
debug kit.
In CY7110, the reset signal is left unconnected because the PMG1-S0 device does not have a reset pin.
Figure 27
10-pin SWD header
3.3.5
MCU I/O header
PMG1 kits have two I/O headers; all GPIOs, PD-specific function signals, regulator output, and other power
signals are routed to these headers. See the pin diagram of the I/O header in each kit explained in the
3.3.6
Reset button
CY7111 EZ-
PD™
PMG1-S1 MCU, CY7112 EZ-
PD™
PMG1-S2 MCU, and CY7113 EZ-PD
™
PMG1-S3 MCU kits have
reset buttons to manually reset the device. When the reset button is pressed, the XRES pin on the device will
pull down to the ground to reset the device. The EZ-
PD™
PMG1-S0 MCU device does not have a reset pin;
therefore, the CY7110 device does not support a manual reset.
RESET
TVS1
ESD3V3D5-TP
No Load
C18
1uF
16V
No Load
SWD_CLK
J8
50MIL KEY ED SMD
No Load
1
3
5
7
9
2
4
6
8
10
VTARG
SWD_IO
