CPU_42A-V1
CPU Board XMC4200 Actuator
Hardware Description
Board User's Manual
18
Revision 1.0, 2013-02-19
2.7.3
Cortex Debug+ ETM Connector (20-pin)
The CPU_42A-V1 board supports Serial Wire Debug operation, Serial Wire viewer operation (via SWO
connection when Serial Wire Debug mode is used) through the 20-pin Cortex Debug+ ETM Connector. The
board does not support the Instruction Trace operation.
JTAG Debug operation additionally would require the TDI (P0.7) signal. By default the TDI signal is
disconnected from the Cortex Debug Connectors by a not assembled resistor R410, because the port pin P0.7
is used by the Actuator boards connected to the ACT satellite connector.
Figure 15 Cortex Debug+ETM Connector (20-pin)
Table 6
Cortex Debug+ ETM Connector (20 Pin)
Pin No.
Signal Name
Serial Wire Debug
JTAG Debug
1
VCC
+3.3 V
+3.3 V
2
SWDIO / TMS
Serial Wire Data I/O
Test Mode Select
3
GND
Ground
Ground
4
SWDCLK / TCK
Serial Wire Clock
Test Clock
5
GND
Ground
Ground
6
SWO / TDO
Trace Data OUT
Test Data OUT
7
KEY
KEY
KEY
8
NC / TDI
Not connected
Test Data IN
9
GNDDetect
Ground Detect
Ground Detect
10
nRESET
Reset (Active Low)
Reset (Active Low)
11
GND/Cap
Ground
Ground
12
TRACECLK
TRACECLK
TRACECLK
13
GND/Cap
Ground
Ground
14
TRACEDATA[0]*
TRACEDATA[0]
TRACEDATA[0]
15
GND
Ground
Ground
cortex_20pin.emf
SWO / TDO / EXTa / TRACECTL
Cortex Debug+ETM
Connector (20-pin)
GNDDetect
SWDIO / TMS
SWDCLK / TCK
1
2
3
4
5
6
7
8
9
10
VCC
GND
GND
KEY
nRESET
11
12
13
14
15
16
17
18
19
20
NC/EXTb/TDI
TRACECLK(NC)
TRACEDATA[0] (NC)
TRACEDATA[1] (NC)
TRACEDATA[2] (NC)
TRACEDATA[3] (NC)
GND/Cap
GND/Cap
GND
GND
GND
