On-Chip Peripheral Components
C513AO
User’s Manual
6-12
05.99
6.1.4 Port Timing
When executing an instruction which changes the value of a port latch, the new value arrives at the
latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by
their output buffers during phase 1 of any clock period (during phase 2, the output buffer holds the
value it noticed during the previous phase 1). Consequently, the new value in the port latch will not
appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle.
When an instruction reads a value from a port pin (such as MOV A, P1), the port pin is actually
sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-11
illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle
is also used if a port pin is to detect an “edge”; for example, when used as a counter input. In this
case, an “edge” is detected when the sampled value differs from the value that was sampled in the
previous cycle. Therefore, certain requirements must be met on the pulse length of signals to avoid
signal “edges” not being detected. The minimum time period of high and low level is one machine
cycle, which guarantees that this logic level is noticed by the port at least once.
Figure 6-11
Port Timing
MCT03231
P1
P2
S4
S5
P2
P1
S6
P2
P1
S1
P2
P1
S2
P2
P1
S3
P2
P1
XTAL2
Input sampled:
e.g. MOV A, P1
Old Data
New Data
Port
P1 active for 1 State
(driver transistor)
