Interrupt System
C513AO
User’s Manual
7-5
05.99
7.2.2 Interrupt Request Flags
The request flags for the different interrupt sources are located in several special function registers.
This section describes the locations and meanings of these interrupt request flags in detail.
External Interrupts 0 and 1 (P3.2/INT0 and P3.3/INT1) each can be either level-activated or
negative transition-activated, depending on bits IT0 and IT1 in SFR TCON. The flags which
generate these interrupts are bits IE0 and lE1 in SFR TCON. When an external interrupt is
generated, the flag that of this interrupt is cleared by hardware when the service routine is vectored
to; but, only if the interrupt was transition-activated. lf the interrupt was level-activated, the
requesting external source directly controls the request flag, rather than the on-chip hardware.
Timer 0 and Timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set by
a rollover in their respective timer/counter registers (all except Timer 0 in Mode 3). When a timer
interrupt is generated, the flag which generated it is cleared by the on-chip hardware when the
service routine is vectored to.
