Infineon AN84858, Quick Start Quide

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Application Note 9 of 45 001-84858 Rev. *N
2021-03-23
PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
This function returns the status byte. Use the status byte to infer error details from the bit field definitions.
See
Figure 2 for the bit fields returned by this function.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SWD ACK [2:0] response
SWD Read Data
Parity Error
SROM Polling Timeout
Port Acquire Timeout
Transition Error
Verification Failure
Figure 2 HSSP Error Status Register
Table 6 describes the bit field definitions of this status register.
Table 6 HSSP Error Status Register
Bit Field Name Description
[2:0] SWD ACK These three bits store the acknowledge response of previous SWD
transactions.
3 SWD Read Data Parity
Error If this bit is set, it indicates a parity error in the data received by the host.
4 Port Acquire Timeout If this bit is set, it indicates that the device was not acquired within the
timeout window.
5 SROM Polling Timeout If this bit is set, It indicates that SROM operations exceed 1 second.
6 Verification Failure This bit is set in multiple steps. Depending upon the step where failure
occurred, the reason can be inferred.
7. Transition Error If this bit is set, it indicates that the chip protection settings read from the
chip and the hex file indicates a wrong transition.
To learn more about this register and for a detailed explanation of the bit fields, see Appendix C: Bit Field
Definitions of HSSP Error Status Register.