XC2200 Derivatives
System Units (Vol. 1 of 2)
Memory Organization
User’s Manual
3-51
V2.1, 2008-08
MemoryX2K, V1.3
3.10
On-Chip Program Memory Control
The internal memory block “IMB” contains all memories of the so called “on-chip program
memory area” in the address range from C0’0000
H
to FF’FFFF
H
. Included are the
program SRAM, the embedded flash memories and central control logic called “IMB
Core”.
In the XC2200 device the IMB contains the following memories:
•
764 KB flash memory in three independent modules.
•
64 KB program SRAM (see
).
The IMB connects these memories to the CPU data bus and the instruction fetch bus.
Each memory can contain instruction code, data or a mixture of both. The IMB manages
accesses to the memories and supports flash programming and erase.
3.10.1
Overview
The
shows how the IMB and its memories are integrated into the device
architecture. Only the main data streams are included. The data buses are usually
accompanied by address and control signals and check-sum data like parity or ECC.
Figure 3-9
IMB Block Diagram
The CPU has two independent busses. The instruction fetch bus is controlled by the
program management unit “PMU” of the CPU. It fetches instructions in aligned groups of
64 bits. The instruction fetch unit of the CPU predicts the outcome of jumps and fetches
IMB
Flash Memory
Flash Module 0
Flash Module 1
Flash Module 2
PSRAM
(Program
SRA M)
IMB
Core
Data
Instructions
64
128
128
imb_block_diagram.vsd
128
16
64
C166SV2
PMU
(Instr fetch)
DMU
(Data access)
CPU
