TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual
6-38
V2.0, 2007-07
Buses, V2.0
6.5.5.2
BCU Error Registers
The capture of bus error conditions is enabled by setting BCU_CON.DBG to 1. In case
of a bus error, information about the condition will then be stored in the BCU error
capture registers. The BCU error capture registers for SPB and RPB can then be
examined by software to determine the cause of the FPI Bus error.
If enabled and a FPI Bus error occurs, the ECON registers holds the captured FPI Bus
control information and an error count of the number of bus errors. The EADD registers
store the captured FPI Bus address. The EDAT registers store the captured FPI Bus
data.
If the capture of FPI Bus error conditions is disabled (BCU_CON.DBG = 0), the BCU
error capture registers remain untouched.
Note: The BCU error capture registers store only the parameters of the first error. In case
of multiple bus errors, an error counter BCU_ECON.ERRCNT shows the number
of bus errors since the first error occurred. A hardware reset clears this bit field to
zero, but the counter can be set to any value through software. This counter is
prevented from overflowing, so a value of 2
16
- 1 indicates that at least this many
errors have occurred, but there may have been more. After BCU_ECON has been
read, the BCU_ECON, BCU_EADD and BCU_EDAT registers are re-enabled to
trace FPI Bus error conditions.
0
[23:20] r
Reserved
Read as 0; should be written with 0.
1) When an access occurs from an SPB bus master to the RPB while the RPB is busy, the SPB bus master has
to wait until the RPB is granted. Therefore, the SBCU time-out value must be larger than the RBCU time-out
value: SBCU_CON.TOUTmin = RBCU_CON.TOUT + 28.
Field
Bits
Type Description
