TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual
25-34
V2.0, 2007-07
ADC, V2.0
25.1.4.1 Conversion Principles
After reset, a power-up calibration is automatically performed in order to correct gain and
offset errors of the A/D Converter. The ongoing power-up calibration is indicated in the
A/D Converter status register by an activated calibrate bit STAT.CAL. To achieve best
calibration results, the reference voltages as well as the supply voltages must be stable
during the power-up calibration.
When a conversion is started, the capacitances of the converter are loaded first via the
respective analog input channel to the analog input voltage. The time to load the
capacitances is referred to as sample time
t
S
. The sample phase is indicated by an
activated status bit STAT.SMPL in the A/D Converter status register. Next, the sampled
voltage is converted to a digital value. Finally, an internal self calibration adapts the
analog converter module to changing temperatures and device tolerances. The
conversion and calibration phase is indicated by the busy signal STAT.BUSY, which
goes inactive at the end of the calibration phase.
Note: During the power-up calibration, no conversion should be started.
25.1.4.2 Conversion Timing Control (CTC and CPS)
The module clock
f
ADC
is generated in the ADC Clock Generation unit (see
). The A/D Converter’s basic operating clock frequency
f
BC
is derived from
f
ADC
via the programmable clock divider CTC, which provides dividing factors from 1:1 to
1:256.
(25.2)
The A/D Converter’s basic operating clock frequency
f
BC
must not exceed 40 MHz. It
must also not drop below 2 MHz.
The internal A/D Converter clock frequency
f
ANA
is a quarter of the basic operating clock
frequency
f
BC
(min. 0.5 MHz, max. 10 MHz). The internal A/D Converter clock
f
ANA
is
related to
f
ADC
according to the following equation:
(25.3)
With the clock control bit field CON.CTC, the internal A/D Converter clock
f
ANA
can be
adjusted to different module timing clock frequencies
f
ADC
in order to optimize the
performance of the TC1796 A/D Converter. Note that CON.CTC may be changed during
a conversion, but will be evaluated after the currently performed conversion is finished.
f
BC
f
ADC
CTC 1
+
----------------------
=
f
ANA
f
BC
4
-----------
1
4
-----
f
ADC
CTC 1
+
----------------------
×
=
=
