Infineon Technologies TC1784, User Manual

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TC1784
Program Memory Unit (PMU)
User´s Manual 5-44 V1.1, 2011-05
PMU, V1.47
For Flash registers separate address spaces are reserved for each PMU (see
Table 5-9 ). The detailed register list of PMU0 is contained in Table 5-3 .
Within the register address table below, the Access Modes “Read” and “Write” indicate
access rights and restrictions as well as values, using symbols as follows:
Note: In the table above, the declaration of access protection with ENDINIT indicates the
standard “ENDINIT” protection feature (including watchdog password access
control) which is used for write accesses to protected system registers. Using this
mechanism, it is possible to change the protected register only before End of
Initialization or after ENDINIT with valid password access to WDT_CON0. Read
accesses are always possible.
The following table shows the addresses, the access modes and reset types for the
Flash registers in PMU0:
Table 5-9 Registers Address Spaces of Flash Registers
Module Base Address End Address Note
FLASH0 F800 1000
H
F800 23FF
H
See Table 5-11
Table 5-10 Address Map Symbols
Symbol Description
U Access permitted in User Mode 0 or 1.
SV Access permitted in Supervisor Mode.
E ENDINIT protected register/address.
BE Indicates that an access to this address range generates a Bus Error.
X Undefined value or bit.
Table 5-11 Addresses of Flash0 Registers
Short
Name Description Address Access Mode Reset See
Read Write
– Reserved F800 2000
H
–F800 2004
H
BE BE – –
FLASH0_
ID Flash Module
Identification Register F800 2008
H
U, SV BE Class3
Reset Page
5-59
– Reserved F800 200C
H
BE BE – –