Infineon Technologies IR3899 User Manual Download Page 2

IRDC3899-P1V2 

9/18/2012 

 
 
 
 
 

                                                        

 

2

 

A well reg12V input supply should be connected to VIN+ and VIN-. A maximum of 9A load should be 
connected to VOUT+ and VOUT-. The  inputs and output connections of the board are listed in Table I.  
 
IR3899 has only one input supply  and internal LDO generates Vcc from Vin. If operation with external Vcc 
is required, then R15 can be removed and  external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin 
and Vcc/LDOout pins should be shorted together for external Vcc operation. 
 
The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero 

ohm  resistor  for  R21).

 

The  value  of  R14  and  R20  can  be  selected  to  provide  the  desired  tracking  ratio 

between output voltage and the tracking input.

 

 

CONNECTIONS and OPERATING INSTRUCTIONS 

LAYOUT 

 

The  PCB  is  a  4-layer  board  (2.23

”x2”)  using  FR4  material.  All  layers  use  2  Oz.  copper.  The  PCB 

thickness is 0.062

”. The IR3899 and other major power components are

 

mounted on the top side of the 

board.  
 
Power  supply  decoupling  capacitors,  the  bootstrap  capacitor    and  feedback  components  are  located 
close to IR3899. The feedback resistors are connected to the output at the point of regulation and are 

located close to the SupIRBuck IC.

 

To improve efficiency, the circuit board is designed to minimize the 

length of the on-board power ground current path.

  

Table I. Connections 

   Connection 

   Signal Name 

VIN+ 

Vin (+12V) 

VIN- 

Ground of Vin 

Vout+ 

Vout(+1.2V) 

Vout- 

Ground for Vout 

Vcc+ 

Vcc/ LDO_out Pin 

Vcc- 

Ground for Vcc input 

Enable 

Enable 

P_Good 

Power Good Signal 

AGnd 

Analog ground 

Summary of Contents for IR3899

Page 1: ...external frequency synchronization with smooth clocking internal LDO and pre bias start up Output over current protection function is implemented by sensing the voltage developed across the on resista...

Page 2: ...vide the desired tracking ratio between output voltage and the tracking input CONNECTIONS and OPERATING INSTRUCTIONS LAYOUT The PCB is a 4 layer board 2 23 x2 using FR4 material All layers use 2 Oz co...

Page 3: ...IRDC3899 P1V2 9 18 2012 3 Connection Diagram Vin Gnd Gnd Vout Enable VDDQ Vref Sync S Ctrl AGnd PGood Vsns Vcc Vcc Top View Bottom View Fig 1 Connection Diagram of IR3899 98 97 Evaluation Boards...

Page 4: ...IRDC3899 P1V2 9 18 2012 4 Fig 2 Board Layout Top Layer Fig 3 Board Layout Bottom Layer Single point connection between AGnd and PGnd...

Page 5: ...IRDC3899 P1V2 9 18 2012 5 Fig 5 Board Layout Mid Layer 2 Fig 4 Board Layout Mid Layer 1...

Page 6: ...ohm SYNC 1 C16 47uF Agnd 1 C17 47uF R7 N A C18 47uF C19 47uF C20 47uF R13 0 ohm C25 N S C23 2 2uF S_Ctrl 1 C12 1nF A 1 B 1 R18 49 9K C1 330uF 25V R50 0 ohm C27 N S VCC C8 2200pF VCC Input ceramic 1206...

Page 7: ...7nF 0603 25V X7R 10 Murata GRM188R71E472KA01J 10 1 C32 1 0uF 0603 25V X5R 10 Murata GRM188R61E105KA12D 11 1 L1 1 0uH SMD 6 36x6 56x3mm 5 62m Coilcraft XAL6030 102ME 12 1 R1 5 23K Thick Film 0603 1 10W...

Page 8: ...Fig 10 Output Voltage Ripple 9A load Ch1 Vout Fig 11 Inductor node at 9A load Ch2 LX Fig 8 Start up at 9A Load Ch1 Vin Ch2 Vo Ch3 Pgood Ch4 Vcc Fig 7 Start up at 9A Load Ch1 Vin Ch2 Vo Ch3 PGood Ch4 E...

Page 9: ...IRDC3899 P1V2 9 18 2012 9 TYPICAL OPERATING WAVEFORMS Vin 12 0V Vo 1 2V Io 0 9A Room Temperature no air flow Fig 13 Transient Response 0A to 3A step Ch1 Vout Ch4 Iout...

Page 10: ...IRDC3899 P1V2 9 18 2012 10 TYPICAL OPERATING WAVEFORMS Vin 12 0V Vo 1 2V Io 0 9A Room Temperature no air flow Fig 14 Bode Plot at 9A load shows a bandwidth of 78 13KHz and phase margin of 55 5 degrees...

Page 11: ...ficiency versus load current TYPICAL OPERATING WAVEFORMS Vin 12 0V Vo 1 2V Io 0 9A Room Temperature no air flow 74 76 78 80 82 84 86 88 90 0 9 1 8 2 7 3 6 4 5 5 4 6 3 7 2 8 1 9 Efficiency Io A 0 0 0 2...

Page 12: ...IRDC3899 P1V2 9 18 2012 12 THERMAL IMAGES Vin 12 0V Vo 1 2V Io 0 9A Room Temperature No Air flow Fig 17 Thermal Image of the board at 9A load Test point 1 is IR3899 Test point 2 is inductor...

Page 13: ...be placed to an accuracy of 0 050mm on both X and Y axes Self centering behavior is highly dependent on solders and processes and experiments should be run to confirm the limits of self centering on s...

Page 14: ...indow in order to accommodate any layer to layer misalignment i e 0 1mm in X Y However for the smaller Signal type leads around the edge of the device IR recommends that these are Non Solder Mask Defi...

Page 15: ...lder paste to make good solder joints with the ground pad high reductions sometimes create similar problems Stencils in the range of 0 125mm 0 200mm 0 005 0 008 with suitable reductions give the best...

Page 16: ...90245 USA Tel 310 252 7105 TAC Fax 310 252 7903 This product has been designed and qualified for the Industrial market Visit us at www irf com for sales contact information Data and specifications sub...

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