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Summary of Contents for 740

Page 1: ... port is brought out to a 3M 26 pin header The RS 232C ports are designed as Data Terminal Equipment DTE to connect directly to a MODEM To connect a terminal directly to the RS 232C port DTE to DTE the RS 232C cable wires must be interchanged for proper operation of terminal S 100 BUS TO I O PROCESSOR INTERFACE 8255A Mode 2 S 100 BUS to Slave Z 80A CPU Interface Due to the drastic reduction of har...

Page 2: ...OUT OUT OUT OUT OUT OUT DEVICE ADDRESS XO X2 OPERATION PORT A S 100 BUS PORT C S 100 BUS XO X2 X3 X3 X3 X3 X3 X3 X3 X3 X3 X3 X3 X3 X3 X3 S 100 S 100 S 100 COH OOH 01H 02H 03H 08H 09H OAH OBH OCH ODH OEH OFH BUS BUS BUS _ 0 1 0 1 0 1 0 1 0 1 0 1 P OR1 POR CON CON PCO PCO PCI PCI PC4 PC4 PCS PCS PC6 PC6 PC7 PC7 CONTROL Mode 2 Control Data Flag Res INT IBF Reset Slave INTE2 INTE for IBF INTE1 INTE fo...

Page 3: ...ndicates that data has been loaded into the input latch of PORT A INTE2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PC4 8255A Definition Summary PAO PA7 I O DATA PBO PB7 UNUSED PCO CONTROL DATA FLAG PCI RESET SLAVE PC2 UNUSED PC3 INTR PC4 STB INTE2 PCS IBF PC6 ACK INTE1 PC7 OBF INTERRÜPT SELECTION OPTION JF JF VIO VII VI2 VI3 VI4 VI5 VI6 VI7 1 2 3 4 5 6 7 8 16 15 14 13 12...

Page 4: ... u i r e s a shunt 4 5 TxCA from RS 232 I n t e r f a c e PIN 15 Signal DB Z 80A SIO PORT B Receive and Transmit Baud dock Selections JB JB 1 6 RxTxCB from Z 80A CTCT l t h i s connection is etched 2 5 RxTxCB from RS 232 I n t e r f a c e PIN 17 Signal DD 3 4 RxTxCB from RS 232 I n t e r f a c e PIN 15 Signal DB S 100 RESET DISABLE SHUNT JD JD 1 2 SHUNT OFF Normal mode J SHUNT ON Local 740 Test mo...

Page 5: ... Ready Data Terminal Ready Ring I n d i c a t o r Data C a r r i e r Detect Transmit Clock Clock From MODEM Receive Clock Clock From MODEM RS 232C Circuit Pin AR D RA DA RR DD r A v A r R vxJD pr vA f T OJJ r f Vxui T R 7v 1 o x 3 _ _ 4 _ _ _ _ _ _ _ c s _ _ _ _ _ _ _ 6 O f t _ __ _ _ O 0 N _ ___ OS o i ti Controller Pin 1 3 5 7 9 DD 17 4 8 IMS INTERNATIONAL D00740 REV 1 0 October 20 1981 Page 9 ...

Page 6: ... CONTROL DATA FLAG 8255A PCS INPUT BUFFER FÜLL 8255A PC7 OUTPUT BUFFER FÜLL RAM PARITY ERROR BELL 801 BELL 801 BELL 801 BELL 801 BELL 801 BELL 801 ROM ENABLE RAM PARITY NUMBER NUMBER NUMBER NUMBER BIT 1 BIT 2 BIT 4 BIT 8 DIGIT PRESENT CALL REQUEST RESET NOTE For more detail regarding the programming of the Z 80AMicrocomputer Components see Zilog Data Book or Technical Manuals IMS INTERNATIONAL D00...

Page 7: ...HD u l 0 O H CC LU Ck 0 o UJ O O cc CL O O O ...

Page 8: ...VIO VII VI2 VI3 VI4 VI5 VI6 VI7 GND A5 A4 A3 DO1 DOO DO4 DO5 DO6 DI2 DI3 DI7 sOUT SINP GND PIN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SIGNAL 8V 16V GND pWR pDBIN AO A1 A2 A6 A7 DO2 DO3 DO7 DI4 DI5 DI6 DI1 DIO POC GND BIS INTERNATIONAL D00740 REV 1 0 October 209 1981 Page 8 ...

Page 9: ..._J o O fc fO CO T l H i i a 4 i i C J 0 00 00 ru f tr 8 Q U O n n T T sTS s S 3 i S S MJ C U f 2 oo T 1 sä Ü i 4 s 4 4 J 4 4 5 33 ul rü i aa csl 3f in o r a o Lü LO QO o K A00740 U UJ i ...

Page 10: ...und Digit Present Abandon Call Retry Call Request Present Next D i g i t Power I n d i c a t i o n Data Set Status Number B i t 1 Number Bit 2 Number Bit 4 Number B i t 8 Data Line Occupied FGD SGD DPR ACR CRQ PND PWI DSS NB1 NB2 NB4 NB8 DLO 1 7 2 3 4 5 6 14 15 17 22 5 9 25 2 4 6 8 o IMS INTERNATIONAL D00740 REV 1 0 October 20 1981 Page 10 ...

Page 11: ...UJ cJ oo r i n OJ J o cJ If SI ol i r v 00 Q Q 00 p 1 Q Q Q IIWT S cC cu r 3 a in fl 3 As 5 CJ l _U n ö 3 1 2 o LÜ Q r CJ 0 e o o ...

Page 12: ...c g r v 9 c M 5 Z _l z_ o 1 o LÜ I Z LO 2 t i i i i K i 2 03 P 2 O et O 00 et O l UJ 0 et Q P v J O _J u_ f _ 0 o 1 ll ...

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Page 14: ...s d t a ll in a ro rxi ra H CO äQ 3 to oQ cd j cc 101 o O f c J in r 9 T c l N j Hh rj fc ä O o Lü l z UO iH 4 s Q o CD Ct O to to ÜJ O o cc CL N O o K e ...

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